Clock dejitter circuit for regenerating DS1 signal

Details Clock dejitter circuit for regenerating DS1 signal Clock dejitter circuit for regenerating DS1 signal

1989-11-17

1991-07-16

Olms, Douglas W.

Pulse or digital communications

Spread spectrum

Direct sequence

370102, H04L 700, H04J 306

Patent

active

050330640

ABSTRACT:
A DS1 dejitter circuit has a control circuit for generating six pulses over a one hundred and ninety three 1.544 Mb/sec clock cycle, and a clock circuit for tracking the frequency of a jittered incoming DS1 signal, and based on that frequency, and utilizing the six pulses, generating a clean DS1 signal at the nominal rate of the jittered incoming signal. The control circuit preferably includes a divide by 28 or 29 circuit which receives a 44.736 Mb/sec (DS3) input clock signal, a mod 193 counter, and a count decoder for providing the six control pulses over the 193 count. Logic circuitry is provided for taking the outputs from the count decode and controlling the divide block to guarantee that the divide block divides the DS3 signal by 29 one hundred eighty-eight times for every five times the divide block divides the DS3 signal by 28. In this manner an average clock of 1.544 Mb/sec (the standard DS1) rate is obtained from the divide block. The clock circuit includes a FIFO, a clock rate control circuit and another divide by 28 or 29 block. The FIFO receives the incoming jittered DS1 signal. The clock rate control circuit senses how full the FIFO is, and using that information along with the pulses from the control circuit regulates the divide block to divide the DS3 signal by 28 either four, five, or six times in a one hundred ninety-three clock cycle. Where it is desired to dejitter a plurality of DS1 signals, a single common control circuit can be used to supply the six control pulses to a plurality of clock rate control circuits.

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