Clock-data recovery (“CDR”) circuit, apparatus...

Details Clock-data recovery (“CDR”) circuit, apparatus... Clock-data recovery (“CDR”) circuit, apparatus...

2003-09-30

2010-02-23

Ghayour, Mohammad H (Department: 2611)

Pulse or digital communications

Synchronizers

Reexamination Certificate

active

07668271

ABSTRACT:
A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

REFERENCES:
patent: 3773975 (1973-11-01), Koziol
patent: 4330862 (1982-05-01), Smolik
patent: 5572558 (1996-11-01), Beherns
patent: 5592109 (1997-01-01), Notani et al.
patent: 5661765 (1997-08-01), Ishizu
patent: 5742798 (1998-04-01), Goldrian
patent: 5754352 (1998-05-01), Behrens et al.
patent: 5838749 (1998-11-01), Casper et al.
patent: 5987238 (1999-11-01), Chen
patent: 6041090 (2000-03-01), Chen
patent: 6104251 (2000-08-01), Ramey et al.
patent: 6285228 (2001-09-01), Heyne et al.
patent: 6307906 (2001-10-01), Tanji et al.
patent: 6366628 (2002-04-01), Su et al.
patent: 6642747 (2003-11-01), Chiu
patent: 6963629 (2005-11-01), Boerstler et al.
patent: 2002/0030522 (2002-03-01), Nakamura
patent: 2003/0128786 (2003-07-01), Schmatz et al.
patent: 02000035831 (2000-02-01), None
Brugel et al., “Variable Bandwidth DPLL Bit Synchronizer with Rapid Acquisition Implemented as a Finite State Machine” IEEE Transactions on Communications, vol. 42, No. 9, Sep. 1994, pp. 2751-2759.

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