Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2007-09-06
2011-10-25
Timory, Kabir A (Department: 2611)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S356000, C375S360000, C375S375000, C375S220000, C375S327000
Reexamination Certificate
active
08045664
ABSTRACT:
A clock/data recovery device1comprises a sampler10, a detector20, an offset determination part30, a clock output part40, and a DA converter50. The phases of clock signals CK and CKX are adjusted so as to match with the phase of an input digital signal. An offset amount (±Voff) added in the sampler10is adjusted so as to match with a peak time of a data transition time distribution of a first signal in a case where a value D(n−1) is HIGH level, and is adjusted so as to match with a peak time of a data transition time distribution of a second signal in a case where the value D(n−1) is LOW level. Either of the clock signals CK and CKX is outputted as the recovered clock signal. Time series data of a digital value D(n) is outputted as the recovered data.
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Sughrue & Mion, PLLC
Thine Electronics Inc.
Timory Kabir A
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