Clock data recovery deserializer with programmable SYNC...

Details Clock data recovery deserializer with programmable SYNC... Clock data recovery deserializer with programmable SYNC...

2006-02-14

2006-02-14

Corrielus, Jean (Department: 2637)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S356000, C375S357000, C375S358000

Reexamination Certificate

active

06999543

ABSTRACT:
In a CDR (clock data recovery) deserializer, a clock divider receives a recovered clock signal (SCLK) and generates a divided clock signal (RPCLK). The frequency of the divided clock signal is lowered with each cycle of the divided clock signal being generated for each count of cycles of the recovered clock signal up to a predetermined ratio number. A serial-to-parallel shift register shifts in recovered serial data bits with each cycle of the recovered clock signal and outputs the predetermined ratio number of the shifted recovered serial data bits at a predetermined transition of every cycle of the divided clock signal. A SYNC (synchronization) detect logic asserts a VRS (diVider ReSet) signal coupled to the clock divider for controlling the clock divider to generate the predetermined transition for a cycle of the divided clock signal when the VRS signal is asserted. The SYNC detect logic includes a plurality of reloadable register portions for storing a plurality of synchronization bit patterns for a plurality of communications protocol. Each of a plurality of bit pattern comparators inputs an intermediate parallel data output (IPDO) from the shift register with each cycle of the recovered clock signal and compares for every cycle of the recovered clock signal the shifted recovered serial data bits to each of the synchronization bit patterns. A multiplexer selects one of the outputs of the bit pattern comparators as the VRS signal depending on the communications protocol of the recovered serial data bits.

REFERENCES:
patent: 5604775 (1997-02-01), Saitoh et al.
patent: 5880973 (1999-03-01), Gray et al.
patent: 5950115 (1999-09-01), Momtaz et al.
patent: 6002717 (1999-12-01), Gaudet
patent: 6031428 (2000-02-01), Hill
patent: 6122336 (2000-09-01), Anderson
patent: 6539051 (2003-03-01), Grivna
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2002/0190751 (2002-12-01), Lee et al.
patent: 2003/0212930 (2003-11-01), Aung et al.
Jason Kontas, “Converting Wide, Parallel Data Buses to High Speed Serial Links,” International IC'99 Conference Proceedings (Apr. 1999).
PCT Publication No. WO 01/69837 A2, published Sep. 20, 2001, Clock Data Recovery Circuit Associated with Programmable Logic Device Circuitry.

Affiliated with

Also associated with

Rating

Clock data recovery deserializer with programmable SYNC... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock data recovery deserializer with programmable SYNC..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock data recovery deserializer with programmable SYNC... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3638797