Clock data recovery circuitry with dynamic support for...

Details Clock data recovery circuitry with dynamic support for... Clock data recovery circuitry with dynamic support for...

2008-02-07

2009-06-30

Bayard, Emmanuel (Department: 2611)

Pulse or digital communications

Synchronizers

Self-synchronizing signal

C375S371000

Reexamination Certificate

active

07555087

ABSTRACT:
Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.

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