Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2007-06-05
2007-06-05
Bayard, Emmanuel (Department: 2611)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
Reexamination Certificate
active
09805843
ABSTRACT:
A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4229825 (1980-10-01), Guidoux
patent: 4680779 (1987-07-01), Wakerly
patent: 5034967 (1991-07-01), Cox et al.
patent: 5084891 (1992-01-01), Ariyavisitakul et al.
patent: 5162762 (1992-11-01), Flanagan
patent: 5184350 (1993-02-01), Dara
patent: 5256918 (1993-10-01), Suzuki
patent: 5357249 (1994-10-01), Azaren et al.
patent: 5457717 (1995-10-01), Bellamy
patent: 5481563 (1996-01-01), Hamre
patent: 5483180 (1996-01-01), Chai et al.
patent: 5552942 (1996-09-01), Ziperovich et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5726988 (1998-03-01), Riley
patent: 5757240 (1998-05-01), Boerstler et al.
patent: 5760844 (1998-06-01), Jorden
patent: 5781038 (1998-07-01), Ramamurthy et al.
patent: 5793822 (1998-08-01), Anderson et al.
patent: 5802103 (1998-09-01), Jeong
patent: 5805632 (1998-09-01), Leger
patent: 5838749 (1998-11-01), Casper et al.
patent: 5896067 (1999-04-01), Williams
patent: 5896561 (1999-04-01), Schrader et al.
patent: 5909126 (1999-06-01), Cliff et al.
patent: 5920600 (1999-07-01), Yamaoka et al.
patent: 5963608 (1999-10-01), Casper et al.
patent: 5974464 (1999-10-01), Shin et al.
patent: 5987543 (1999-11-01), Smith
patent: 5999025 (1999-12-01), New
patent: 6008680 (1999-12-01), Kyles et al.
patent: 6031428 (2000-02-01), Hill
patent: 6031473 (2000-02-01), Kubinec
patent: 6091261 (2000-07-01), De Lange
patent: 6092210 (2000-07-01), Larky et al.
patent: 6104732 (2000-08-01), Pearman
patent: 6166572 (2000-12-01), Yamaoka
patent: 6178213 (2001-01-01), McCormack et al.
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6223089 (2001-04-01), Page
patent: 6256722 (2001-07-01), Acton et al.
patent: 6259271 (2001-07-01), Couts-Martin et al.
patent: 6266799 (2001-07-01), Lee et al.
patent: 6292116 (2001-09-01), Wang et al.
patent: 6295563 (2001-09-01), Whittaker
patent: 6327196 (2001-12-01), Mullarkey
patent: 6341142 (2002-01-01), Ducaroir et al.
patent: 6374361 (2002-04-01), Lee et al.
patent: 6400291 (2002-06-01), Sankey
patent: 6421796 (2002-07-01), Gatherer
patent: 6437713 (2002-08-01), Lesea
patent: 6463109 (2002-10-01), McCormack et al.
patent: 6538656 (2003-03-01), Cheung et al.
patent: 6631144 (2003-10-01), Johansen
patent: 6650720 (2003-11-01), Grung et al.
patent: 6724328 (2004-04-01), Lui et al.
patent: 6771105 (2004-08-01), Andrasic et al.
patent: 6832173 (2004-12-01), Starr et al.
patent: 6834367 (2004-12-01), Bonneau et al.
patent: 6854044 (2005-02-01), Venkata et al.
patent: 6917661 (2005-07-01), Scott et al.
patent: 7138837 (2006-11-01), Venkata et al.
patent: 2 011 764 (1979-07-01), None
patent: 63-121344 (1988-05-01), None
patent: 63-108238 (1988-07-01), None
patent: 4-199912 (1992-07-01), None
patent: 04287439 (1992-10-01), None
patent: 05199107 (1993-08-01), None
patent: 6-48243 (1994-06-01), None
patent: 6-327072 (1994-11-01), None
patent: 7-58731 (1995-03-01), None
patent: 08032569 (1996-02-01), None
patent: 9-149017 (1997-06-01), None
patent: 10-134523 (1998-05-01), None
patent: 11-317730 (1999-11-01), None
patent: 11-317731 (1999-11-01), None
Lemme, Helmuth, “Schnelle Chips Für Flaschenhälse” Elektonik, Franzis Verlag GMBH. Munchen, DE, vol. 40, No. 22, Oct. 29, 1991, pp. 104-109.
Cook, Barry M., “IEEE 1355 Data-Strobe Links: ATM Speed at RS232 Cost”, Microprocessors and Microsystems, Mar. 30, 1998, Elsevier, UK, vol. 21, No. 7-8, pp. 421-428.
Konstas, Jason, “Converting Wide, Parallel Data Buses to High Speed Serial Links”, Cypress Semiconductor, 1999, pp. 19-30.
“Protocol Independent Gigabit Backplane Transceiver Using Lucent ORT4622/ORT8850 FPSCs”, Application Note, Jun. 2000, Lucent Technologies Inc., pp. 1-10.
“Lucent Introduces 10Gb/s Ethernet FPGAs”, Programmable Logic News and Views, Electronic Trend Publications, Inc., vol. IX, No. 11, Nov. 2000, pp. 7-8.
“ORCA ORT82G5 0.622/1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC”, Product Brief, Feb. 2001, Lucent Technologies Inc., pp. 1-8.
U.S. Appl. No. 09/516,921, filed Mar. 2, 2000, Ngai et al.
Charles R. Hogge, Jr., “A Self Correcting Clock Recovery Circuit,” IEEE Transactions On Electron Devices, vol. ED-32, No. 12, pp. 2704-2706, Dec. 1985.
Timothy H. Hu et al., “A Monolithic 480 Mb/s parallel AGC/Decision/Clock-Recovery Circuit in 1.2-μm CMOS,” IEEE Journal Of Solid-State Circuits, vol. 28, No. 12, Dec. 1993.
Ilya I. Novof et al., “Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ±50 ps Jitter,” IEEE Journal Of Solid-State Circuits, vol. 30, No. 11, pp. 1259-1266, Nov. 1995.
Ricardo Monleone, “Clock-recovery PLL fits into single PLD,” EDN, pp. 88-92, Nov. 23, 1995.
Fong, Thomas Kin Tak, “Advanced clock recovery techniques for high-speed packet-switched optical networks,” ProQuest, Abstract (Document Summary), 1995.
M. Rau, et al., “Clock/Data Recovery PLL Using Half-Frequency Clock,” IEEE Journal Of Solid-State Circuits, vol. 32, No. 7, Jul. 1997.
German Gutierrez et al., “Unaided 2.5 Gb/s Silicon Bipolar Clock and Data Recovery IC,” IEEE Radio Frequency Integrated Circuits Symposium, VIII-7, pp. 173-176, 1998.
Ankit Seedher et al., “Fractional Rate Phase Detectors for Clock and Data Recovery,” IEEE, pp. 313-316, 2003.
U.S. Appl. No. 10/059,014, filed Jan. 29, 2002, Lee et al.
U.S. Appl. No. 10/273,899, filed Sep. 16, 2002, Venkata et al.
U.S. Appl. No. 10/317,264, filed Dec. 10, 2002, Venkata et al.
Aung Edward
Butler Paul
Lee Chong
Lui Henry
Patel Rakesh
Altera Corporation
Bayard Emmanuel
Chasan Michael J.
Jackson Robert R.
LandOfFree
Clock data recovery circuitry associated with programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock data recovery circuitry associated with programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock data recovery circuitry associated with programmable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3807094