Clock data recovery circuit with improved jitter transfer...

Details Clock data recovery circuit with improved jitter transfer... Clock data recovery circuit with improved jitter transfer...

2005-06-07

2005-06-07

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

C375S362000, C370S509000

Reexamination Certificate

active

06903587

ABSTRACT:
A clock extracting part has a first phase comparator circuit, a first up/down counter, a weighting circuit, a charge pump and a low-pass filter forming a voltage value determining part, and a voltage controlled oscillator circuit. A retiming clock generating part has a second up/down counter and a phase switching circuit. Furthermore, a phase adjusting part has a first counter, a second counter, a second phase comparator circuit and a third up/down counter forming a phase adjusting part. A clock data recovery circuit is formed by said clock extracting part, the retiming clock generating part, the phase adjusting part, and a first-in first-out memory part. Thereby, a clock data recovery circuit is obtained, in which jitter transfer characteristics and jitter tolerance satisfy the standards of both the SONET and SDH.

REFERENCES:
patent: 5128939 (1992-07-01), Takatori et al.
patent: 5146477 (1992-09-01), Cantoni et al.
patent: 5202904 (1993-04-01), Kamada
patent: 5271006 (1993-12-01), Ashi et al.
patent: 5357514 (1994-10-01), Yoshida
patent: 5390180 (1995-02-01), Reilly
patent: 5831461 (1998-11-01), Dawe
ISSCC 2002, Session 15, Gigabit Communications, Jun Cao et al., “OC-192 Receiver in Standard 0.18 μm CMOS”, 2002, pp. 1-3.

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