Clock data recovery circuit capable of generating clock...

Details Clock data recovery circuit capable of generating clock... Clock data recovery circuit capable of generating clock...

2006-06-30

2010-10-26

Torres, Juan A (Department: 2611)

Pulse or digital communications

Synchronizers

C370S503000, C327S141000, C327S165000

Reexamination Certificate

active

07822158

ABSTRACT:
A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

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Tatsuya Saito et al., A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface Using Novel Eye-tracking Method, 2003 Symposium on VLSI Circuits Digest of Technical Papers, pp. 57-60.

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