Clock/data recovery circuit

Details Clock/data recovery circuit Clock/data recovery circuit

2006-08-22

2006-08-22

Ha, Dac (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C327S156000, C327S141000, C370S395620, C370S503000, C370S535000, C375S354000, C375S376000

Reexamination Certificate

active

07095816

ABSTRACT:
A clock/data recovery circuit used in a receiving apparatus is provided in the circuit including: a voltage control oscillator for generating a clock signal of a frequency of 1/K of a bit rate of an input data signal; a delay circuit; a demultiplexer for demultiplexing the input data signal; a multiplexer for multiplexing the demultiplexed signals; a phase comparator for comparing phases of an output signal of the delay circuit and an output signal of the multiplexer; a lowpass filter; wherein the clock/data recovery circuit outputs the clock signal generated by the voltage control oscillator as a recovery divided clock signal, and outputs the demultiplexed signals output as recovery parallel data signals.

REFERENCES:
patent: 5001711 (1991-03-01), Obana et al.
patent: 5703511 (1997-12-01), Okamoto
patent: 5933058 (1999-08-01), Pinto et al.
patent: 6178213 (2001-01-01), McCormack et al.
patent: 6259755 (2001-07-01), O'Sullivan et al.
patent: 6333678 (2001-12-01), Brown et al.
patent: 6359519 (2002-03-01), Farrow
patent: 6671342 (2003-12-01), Lin et al.
patent: 6809562 (2004-10-01), Wada et al.
patent: 5-56410 (1993-03-01), None
patent: 06252654 (1994-09-01), None
patent: 10126400 (1998-05-01), None
patent: 10-285150 (1998-10-01), None
patent: 11055082 (1999-02-01), None
Noboru Ishihara, Yukio Akazawa, “A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit Using the Sample-and-Hold Technique”, IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994, pp. 1566-1571.
D. Clawin, U. Langmann, “Multigigabit/second Silicon Decision Circuit”, ISSCC 85, Feb. 1985, pp. 222-223.
M. Wurzer, J. Bock, W. Zirwas, H. Knapp, F. Schumann, A. Felder, L. Treitinger, “40Gb/s Integrated Clock and Data Recovery Circuit in a Silicon Bipolar Technology”, IEEE BCTM 8.1, Sep. 27-29, 1998.
J. Savoj, B. Razavi, “A 10 Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection”, ISSCC 2001, Feb. 5, 2001.
D. Clawin, U. Langmann, B.G. Bosch, “Silicon Bipolar Decision Circuit Handling Bit Rates up to 5Gbit/s”, Journal of lightwave technology, vol. LT-5, No. 3, Mar. 1987, pp. 348-354.
Müllner et al., “A 20 Gbit/s Parallel Phase Detector and Demultiplexer Circuit in a Production Silicon Bipolar Technology with fT=25 GHz”, BIPOLAR/BICMOS Circuits and Technology Meeting, IEEE, Sep. 29, 1996, pp. 43-45.
J. Savoj, B. Razavi, “A 10 Gb/s CMOS Clock and Data Recovery Circuit”, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 136-139.
International Search Report, EP 02 25 1533, Oct. 13, 2005.
M. Wurzer et al., “A 40-Gb/s Integrated Clock and Data Recovery Circuit in a 50-GHz Silicon Bipolar Technology,” IEEE J. Solid-State Circuits, vol. 34, No. 9, pp. 1320-1324 Sep. 1999.

Affiliated with

Also associated with

Rating

Clock/data recovery circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock/data recovery circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock/data recovery circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3639143