Clock data recovery circuit

Details Clock data recovery circuit Clock data recovery circuit

2011-07-19

2011-07-19

Ha, Dac V (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

C375S327000, C375S373000, C375S376000, C375S293000, C327S156000, C327S012000, C327S157000, C327S212000, C327S211000, C331S057000, C331S1170FE, C331S10800D, C331S167000, C331S187000

Reexamination Certificate

active

07983361

ABSTRACT:
A clock data recovery circuit. The clock data recovery circuit comprises a transmission line, a phase locked loop, a voltage controlled oscillator, a phase selector, and a D flip-flop. The transmission line receives an input signal. The phase locked loop receives the input signal via the transmission line and a reference clock and generates a first clock signal. The voltage controlled oscillator receives the input signal via the transmission line and a control voltage from an internal node of the phase locked loop, and generates a clock signal. The phase selector receives the input signal via the transmission line and the clock signal from the voltage controlled oscillator, and generates a clock output signal. The D flip-flop receives the input signal via the transmission line and the clock output signal, and generates a data output signal.

REFERENCES:
patent: 5206607 (1993-04-01), Shiga
patent: 5557224 (1996-09-01), Wright et al.
patent: 6807117 (2004-10-01), Eguchi
patent: 6867626 (2005-03-01), Idei
patent: 7333570 (2008-02-01), Aung et al.
patent: 2005/0206465 (2005-09-01), Okamoto

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