Clock data recovering system with external early/late input

Details Clock data recovering system with external early/late input Clock data recovering system with external early/late input

2007-12-28

2008-08-26

Ahn, Sam K (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

Reexamination Certificate

active

07418069

ABSTRACT:
The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.

REFERENCES:
patent: 6570944 (2003-05-01), Best et al.
Gabara, an 0.25 um CMOS Injection Locked 5.6Gb/s Clock and Data Recovery Cell, Integrated Circuits and Systems Design, 1999, p. 84-87.

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