Clock data recovering system with external early/late input

Details Clock data recovering system with external early/late input Clock data recovering system with external early/late input

2008-01-01

2008-01-01

Payne, David C. (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S371000

Reexamination Certificate

active

07315594

ABSTRACT:
The invention is directed to a clock data recovery system for resampling a clock signal to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependant on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.

REFERENCES:
patent: 5134637 (1992-07-01), Beyer et al.
patent: 5761254 (1998-06-01), Behrin
patent: 6266799 (2001-07-01), Lee et al.
patent: 0 317 159 (1989-05-01), None
patent: 0317159 (1989-05-01), None
patent: 0317159 (1989-05-01), None
patent: 0317159 (1989-05-01), None
International Preliminary Examination Report, dated Nov. 27, 2003.
International Preliminary Examination Report, dated Aug. 20, 2003.

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