Clock converting circuit

Details Clock converting circuit Clock converting circuit

1998-06-29

2000-07-04

Nguyen, Minh

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

327271, 327284, H03K 708

Patent

active

060844531

ABSTRACT:
A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.

REFERENCES:
patent: 4634984 (1987-01-01), Harwood et al.
patent: 5699003 (1997-12-01), Saeki
patent: 5708382 (1998-01-01), Park
"A 2.5 ns Clock Access 250MH.sub.z 256Mb SDRAM with a Synchronous Mirror Delay", 1996 IEEE International Solid-State Circuits Conference, Technical Digest, pp. 374-375, T. Saeki et al. Date Feb. 1996.

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