Clock converter circuit

Details Clock converter circuit Clock converter circuit

1976-03-08

1976-11-23

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307216, 307208, 307225R, 328 16, 328 56, H03K 500

Patent

active

039939570

ABSTRACT:
This invention discloses a structure whereby a fixed frequency machine clocking signal can be multiplied in frequency by any desired integral value. The device uses a tapped delay line having a total time delay slightly less than the time of one-half cycle of the clocking signal and an exclusive-OR tree connected to the taps of the delay line to generate a higher frequency output clock signal. By interposing a known frequency division network to the input of the delay line, the output clock signal can be generated with any desired rational relationship to the driving clocking signal.

REFERENCES:
patent: 3226647 (1965-12-01), Shirman
patent: 3386036 (1968-05-01), Gerrard et al.
IBM Tech Disclosure Bull. by Widmer, vol. 6, No. 9, Feb. 1964, pp. 71-72.

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