Clock controlling method and circuit

Details Clock controlling method and circuit Clock controlling method and circuit

2002-09-09

2003-09-16

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

06621317

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a clock control circuit and a clock control method.
BACKGROUND OF THE INVENTION
A PLL (phase locked loop) circuit is used in a circuit for adjusting a clock period.
FIG. 27
illustrates a conventional PLL circuit. Referring to
FIG. 27
, a phase frequency detector (PFD)
319
receives an external clock
324
and a signal supplied from a frequency divider
323
that receives an output of a voltage-controlled oscillator
322
. A charge pump
320
receives a up signal
325
and a down signal
326
both output from a phase frequency detector (PFD)
319
to output a voltage corresponding to a phase difference. A loop filter receives the voltage from the charging pump
320
to output smoothed voltage which is supplied as a control voltage to the voltage-controlled oscillator (VCO)
322
. An output clock signal of a frequency corresponding to the control voltage from the voltage-controlled oscillator (VCO)
322
is fed to a frequency divider
323
.
For example, there is proposed in JP Patent Kokai JP-A-11-284497 a programmable delay generator in which a ramp waveform voltage for determining a delay time and a threshold voltage can be generated by circuits of the same structure and can be independently set so that it is capable of generating the delay time of a fractional number, a numerator and a denominator of which can be set, a frequency synthesizer which, by phase-interpolating output pulses of an accumulator using a programmable delay generator, is able to generate an adjustment-free low-spurious output signal, a multiplication circuit employing a programmable delay generator, a duty ratio converter circuit employing the programmable delay generator as an output pulse width setting delay generator, and a PLL frequency synthesizer having the programmable delay generator inserted between the frequency divider and a phase comparator.
SUMMARY OF THE DISCLOSURE
However, the conventional circuit, as shown in
FIG. 27
, employing, a PLL circuit and a feedback type circuit, has drawbacks that phase adjustment operation is time-consuming and that there exists a jitter (phase noise) proper to a feedback system.
Moreover, the above-described conventional programmable delay generator is in need of a power source voltage generating circuit, such as a threshold voltage generating circuit, and hence the circuit scale is increased.
It is therefore an object of the present invention to provide a clock control circuit and a clock control method whereby non-integer frequency conversion can be effected with a high degree of accuracy by a simplified configuration.
For accomplishing the above object, one aspect of the present invention is a configuration in which a clock is input and an output clock having a phase difference relative to the input clock, the phase obtained by adding or subtracting to or from said phase by a predetermined unit value of a phase differential, on each constant period, is output.
In accordance with another aspect of the present invention, a clock control circuit comprises control means for outputting a control signal for adding or subtracting to or from the phase of an output signal relative to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and phase adjustment means fed with the input clock for generating and outputting output clock having a phase corresponding to adding or subtracting a preset unit value of a phase differential to or from a phase with respect to the reference clock, based on the control signal, whereby an output clock of a frequency in a non-integer relation to the frequency of the reference clocks can be output.
Another aspect of the present invention is a clock control circuit comprising a frequency divider for outputting frequency-divided clock obtained on frequency dividing the input clock, a control circuit for generating a control signal for adding or subtracting a unit phase difference to or from the input clock with respect to the frequency-divided clock based on the frequency divided clock output from the frequency divider and a phase adjustment circuit fed with the input clock and generating and outputting an output clock having a phase prescribed by the control signal from the control circuit.
Another aspect of the present invention is a clock control circuit comprising a multi-phase clock generating circuit for generating and outputting first to nth clocks having respective different phases (multi-phase clocks) from a phase of the input clock, a selector fed with the first to nth clocks to selectively output one of the clocks, and a control circuit fed with the input clock to generate a control signal sequentially selecting the first to nth clocks to send the generated selection signal to the selector.
Another aspect of the present invention is a clock control circuit comprising an interpolator receiving a frequency divided signal produced by a frequency dividing circuit receiving a clock signal and a signal obtained by shifting the frequency divided signal in a preset number of periods of the clock to produce a signal obtained on division of a timing difference of said two input signals at a preset ratio of internal division; and
a control circuit for varying the value of the ratio of the internal division of the timing difference in said interpolator based on said clock signals.
Another aspect of the present invention is a clock control circuit comprising a plurality of (N) interpolator-s for outputting signals obtained on dividing a timing difference of two input signals with respective different values of a preset ratio of internal division; wherein of first to nth clocks with respective different phases, two clocks, that is the Ith and the (I+1)st clocks, where I is an integer from 1 to N, with N+1 being 1, are input to the Ith interpolator.
In accordance with another aspect of the present invention, the interpolator comprises a logic circuit fed with first and second input signals to output a result of preset logical processing of said first and second input signals;
a first switching device connected across a first power source and an internal node, said first switching device being fed at a control terminal thereof with an output signal of said logic circuit and being turned on when said first and second input signals are both of a first value;
a buffer circuit having an input terminal connected to said internal node and having an output logical value changed on inversion of relative magnitudes of the terminal voltage of the capacitance of said internal node and a threshold value;
a plurality of serial circuits connected across said internal node and a second power source in parallel, each of said serial circuits being made up of a second switching device turned on when said first input signal is of a second value, said third switch device turned on or off based on a control signal from said control circuit, and a first constant current source; and
a plurality of serial circuits connected across said internal node and a second power source in parallel, each of said serial circuits being made up of a fourth switching device turned on in common when said first input signal is of a second value, said fifth switching device turned on or off based on a control signal from said control circuit, and a constant current source.
In accordance with another aspect of the present invention, said interpolator comprises a logic circuit receiving first and second input signals to output results of preset logical processing of said first and second input signals;
a first switching device connected across a first power source and an internal node, said first switching device being fed at a control terminal thereof with an output signal of said logic circuit and being turned on when said first and second input signals are both of a first value; and
a buffer circuit having an input end connected to said internal node and having an output logical value changed on inversion of the relative magnitudes of the termin

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