Clock-controlled gate circuit

Details Clock-controlled gate circuit Clock-controlled gate circuit

1975-08-05

1976-12-21

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307214, 307215, H03K 1908, H03K 1934, H03K 1936, H03K 1940

Patent

active

039990818

ABSTRACT:
A clock-controlled gate circuit employs field-effect transistors of both n- and p-type conductivities. The circuit includes a precharge circuit, a logic circuit, and a switching transistor serially connected in that order between a power source and ground and a capacitor is connected to the junction between the precharge circuit and the logic circuit.

REFERENCES:
patent: 3518451 (1970-06-01), Booher
patent: 3551692 (1970-12-01), Yen
patent: 3601627 (1971-08-01), Booher
patent: 3631261 (1971-12-01), Heimbigner
patent: 3798617 (1974-03-01), Varadi
patent: 3829710 (1974-08-01), Hirasawa et al.
Yen, "Computer-Aided Test Generation for Four-Phase MOS LSI Circuits", IEEE Trans. on Computers, vol. C-18, No. 10, pp. 890-894, 10/1969.
Nomiya et al., Def. Pub. Search Copy of Serial No. 381,484, filed July 23, 1973, published in 926 O.G. 9, on Sept. 3, 1974, Def. Pub. No. T926,003.

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