Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1997-09-08
2001-08-28
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S155000
Reexamination Certificate
active
06281733
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock control method and an integrated circuit element (hereinafter referred to as an IC), and particularly relates to an IC using a clock in the internal circuit thereof and a method of controlling the clock inside the IC.
2. Description of the Prior Art
The integration of circuits carries advantages of reduced packaging area through an increased degree of the integration and reduced cost manufacturing through a decreased number of components. As one example, a microcomputer having a clock generating circuit built therein is given on page 89 of “Hitachi Single-Chip RISC Microcomputer SH7032, SH7034, HD6417032, HD6477034, HD6437034 Hardware Manual (third edition)”.
FIG. 2
is a circuit diagram regarding a clock of this microcomputer.
As shown in
FIG. 2
, the circuit has two input terminals XTAL
2
and EXTAL
4
, via which a signal is input and then transmitted to an oscillator
6
. The input terminals XTAL and EXTAL are also connected to a crystal oscillator and a capacitive circuit in a known manner. A clock is oscillated by the oscillator
6
, shaped in a duty correction circuit
8
, and then supplied to the internal circuit of the microcomputer and an output terminal CK
10
. The output terminal CK in turn supplies the clock to an external system of the microcomputer.
According to the microcomputer, the provision of the built-in oscillator
6
can decrease the number of components constituting the circuit, and the same clock can be used in the internal circuit and the external system. Therefore, timings can easily be controlled, both inside and outside the microcomputer.
As another advantage of the circuit integration, there is a high-speed operation of the circuit. In general, the delay of a gate in the IC is smaller than that of the equivalent external logic circuit constituted by discrete components. By incorporating the main part of the circuit into a single IC, the operation speed of the entire device is improved.
In order to improve operation speed, the employment of a high speed (high frequency) clock is necessary. When the high-speed clock is used, however, a problem of clock skew occurs. Clock skew refers to a deviation in timings of clocks, which should be originally the same, caused by gating or dividing the clocks. When a low-speed clock is used, in order to eliminate the clock skew, a delay gate can be incorporated in a relatively advanced clock, or other countermeasure can be taken. However, for example, in the 50 MHz clock having one cycle of only 20 ns, adjustment by means of the delay gate is limited. On the spot of design, there is a daily situation that even if one place is corrected, a timing violation arises in another place. When high-speed circuit operation is desired, avoiding malfunction caused by clock skew is important, but it is a remarkably intricate and laborious work.
In the aforementioned microcomputer, the clock appearing at the external terminal CK is delayed as much as an output buffer, as compared with the clock used in the internal circuit. When this microcomputer is manufactured so as to operate at, for example, 50 MHz, the delay of the output buffer is usually about several ns, which would produce a critical clock skew inside and outside the microcomputer as the case may be. Additionally, since the advanced clock is used in the microcomputer, the adjustment of timings by means of the external delay gate is usually unfeasible.
SUMMARY OF THE INVENTION
Wherefore, an object of the present invention is to provide a method in which clock skews inside and outside an IC are reduced and the IC using the method.
Another object of this invention is to control a clock with a minimum number of terminals.
A further object of this invention is to flexibly perform a clock control test on a circuit.
To attain these and other objects, the invention provides the following clock control method and IC.
(1) Clock Control Method
In the invention, the clock existing in the IC is output once via the output path of an input/output buffer and returned via the input path of the same input/output buffer into the IC. This clock is used in the internal circuit of the IC.
Therefore, both the clocks used inside and outside the IC pass an output buffer in the input/output buffer. The clock returned into the IC passes an input buffer in the input/output buffer. The delay of the input buffer is usually smaller than that of the output buffer. If the other conditions are the same, clock skews are decreased in the circuit as compared with the circuit of FIG.
2
. In the circuit of
FIG. 2
, the greater the load on the external circuit is, the more skews are produced. In the invention, however, skews are independent of the external load. Further in the invention, the clock inside the IC is delayed as much as the input buffer, and the delay can be advantageously adjusted easily outside the IC.
Another advantage of this method lies in that the same input/output buffer is used for the output and reentry of the clock. A single input/output buffer means only one terminal. Therefore, the terminal can be effectively used.
(2) Clock Control IC
The invention provides an IC using a clock in the internal circuit thereof. The IC includes a clock generator, an input/output buffer for supplying the generated clock to an output path, and a selector for selecting either a signal in the input path of the input/output buffer or the clock. The selected signal is supplied to the internal circuit as an internal clock.
In operation of the structure, a clock is first generated in the clock generator. This clock is supplied to the output path of the input/output buffer, i.e. the input side of an output buffer. On the other hand, the input path of the input/output buffer, i.e. the output side of an input buffer is connected to the input of the selector. Therefore, in the selector, either the first generated clock or the output and returned clock (hereinafter referred to as the reentry clock) is selected and output. If the reentry clock is selected, clock skews are decreased inside and outside the IC, because the selected clock is given to the internal circuit of the IC.
Another advantage of this structure lies in that, not only the reentry clock, but also the first generated clock, can be selected. Specifically, when the problem is the wave form of the clock to be used inside the IC, rather than the clock skew inside and outside the IC, the first generated clock is preferable to the reentry clock because the reentry clock is deformed by the external circuit component.
As mentioned above, the clock is generated inside the IC in the invention. Alternatively, a clock is input via an input terminal, and the clock resulting from the input clock can be supplied to the output path of the input/output buffer. The clock resulting from the input clock includes the input clock itself and the input clock divided or otherwise processed inside the IC.
REFERENCES:
patent: 4626716 (1996-05-01), Miki
patent: 4637018 (1987-01-01), Flora et al.
patent: 4761567 (1988-08-01), Walters, Jr. et al.
patent: 5065042 (1991-11-01), Thomsen et al.
patent: 5220217 (1993-06-01), Scarra et al.
patent: 5517638 (1996-05-01), Szczepanek
patent: 5751175 (1998-05-01), Imamura
patent: 5754069 (1998-05-01), Nagarajai
“Hitachi Single-Chip RISC Microcomputer SH7032, SH7034, HD6417032, HD6477034, Hardware Manual” (Third Edition), Copyright 1993.
Koumura Yasuhito
Matsumoto Kenshi
Miura Hiroki
Callahan Timothy P.
Hogan & Hartson LLP
Sanyo Electric Co,. Ltd.
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