Clock control circuits, systems and methods

Details Clock control circuits, systems and methods Clock control circuits, systems and methods

1997-05-08

1998-11-24

Butler, Dennis M.

395560, G06F 104, G06F 108

Patent

active

058420053

ABSTRACT:
A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

REFERENCES:
patent: 5184032 (1993-02-01), Leach
patent: 5388265 (1995-02-01), Volk
patent: 5473767 (1995-12-01), Kardach et al.
patent: 5497482 (1996-03-01), Keida et al.
patent: 5710911 (1998-01-01), Walsh et al.

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