Clock control circuit with an input stop circuit

Details Clock control circuit with an input stop circuit Clock control circuit with an input stop circuit

2000-02-14

2001-03-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C327S158000, C327S159000, C327S161000, C327S299000, C327S154000

Reexamination Certificate

active

06198690

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-035946, filed Feb. 15, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a clock control circuit most suitable for a circuit subjected to synchronization control using a high-speed clock signal.
In recent years, a clock sync-type memory such as a synchronous DRAM has sometimes been used to meet the demand for a high processing speed of a computer system. Such a clock sync-type memory device uses an internal clock signal in synchronism with a clock signal input thereto for controlling the memory.
In the case where a delay occurs between the internal clock signal used in the memory device and an external clock signal input from an external source for controlling the memory device, the internal circuits of the memory device high in operating speed are liable to develop a malfunction even if the delay is small.
In view of this, a semiconductor integrated circuit such as a memory device using a clock signal includes a clock control circuit built in a memory integrated circuit for assuring synchronism between the internal clock signal and the external clock signal. First, the operating principle of this clock control circuit will be explained.
FIG. 1
shows a clock control circuit of synchronous adjustable delay (SAD) type including a synchronous traced backward delay (STBD) disclosed in U.S. Pat. No. 5,867,432 granted to Haruki Toda. This clock control circuit of SAD type is well known for its high sync speed and small power consumption. The contents of which are incorporated herein by reference in their entirely.
The circuit of
FIG. 1
includes a clock receiver
11
, a delay monitor circuit
12
, a forward pulse delay circuit
14
having a plurality of delay circuits
13
connected in a multiplicity of stages in cascade, a backward pulse delay circuit
16
having delay circuits
15
connected in a multiplicity of stages in cascade in the same number as stages of the delay circuits
13
in the forward pulse delay circuit
14
, and a state-hold section
18
having a plurality of state-hold circuits
17
as many as the delay circuits arranged in the forward pulse delay circuit
14
and the backward pulse delay circuit
16
for outputting a control signal for controlling the pulse delay operation in the backward pulse delay circuit
16
in accordance with the pulse delay state of the forward pulse delay circuit
14
, a control signal generating circuit
19
for outputting control signals P, /P for controlling the operation of the forward pulse delay circuit
14
and the state-hold section
18
, and a driver
20
.
The output from the delay circuit
13
in the Nth stage in the forward pulse delay circuit
14
is input to the Nth-stage state-hold circuit
17
in the state-hold section
18
, and the output from the Nth-stage state-hold circuit
17
in the state-hold section
18
is input to the (N−1)th-stage delay circuit
15
in the backward pulse delay circuit
16
.
FIG. 2
is a timing chart for explaining the operating principle of the clock control circuit shown in FIG.
1
. With reference to
FIGS. 1 and 2
, the operating principle of the conventional clock control circuit will be explained.
Now, assume that an external clock signal ExtCLK having a cycle of &tgr; is input to the clock receiver
11
. The external clock signal ExtCLK is shaped in waveform and amplified by the receiver
11
and output as a pulse signal CLK. In the case where a delay time in the clock receiver
11
is Trc, the pulse signal CLK is delayed by Trc behind the external clock signal ExtCLK, as shown in FIG.
2
. The pulse signal CLK output from the receiver
11
is input to the delay monitor circuit
12
, the control signal generating circuit
19
and the backward pulse delay circuit
16
.
The control signal generating circuit
19
receives the pulse signal CLK, and as shown in
FIG. 2
, outputs a control signal P having a pulse width Wp in synchronism with the leading edge of the pulse signal CLK. Though not shown, the control signal generating circuit
19
outputs, together with the control signal P, a control signal /P having a level complementary with the control signal P. Where a delay time in the driver
20
is Tdr, the pulse width Wp of the control signal P is set shorter than the period (Trc+Tdr). The reason is that if the width Wp of the control signal P is longer than (Trc+Tdr), the output from the delay monitor circuit
12
fails to correctly propagate through the forward pulse delay circuit
14
.
The delay monitor circuit
12
has a delay time (Trc+Tdr) equal to the sum of the delay time Trc in the receiver
11
and the delay time Tdr in the driver
20
. Thus, the pulse signal FCL output from the delay monitor circuit
12
, as shown in
FIG. 2
, is delayed by (Trc+Tdr) behind the pulse signal CLK output from the receiver
11
and input to the forward pulse delay circuit
14
.
The forward pulse delay circuit
14
is configured with a plurality of delay circuits
13
connected in a multiplicity of stages in cascade. The delay circuit
13
in each stage transmits a forward pulse signal to the succeeding stage from the preceding stage when the control signal P is “L”, while the transmission of the forward pulse signal is stopped when the control signal P is “H”.
During the period {&tgr;−(Trc+Tdr)} from the time point when the transmission is started of the pulse signal FCL through the forward pulse delay circuit
14
to the time when the control signal P rises to “H” level, the pulse signal FCL is transmitted through the forward pulse delay circuit
14
.
The state-hold section
18
stores the transmission state of the forward pulse signal through the forward pulse delay circuit
14
in each state-hold circuit
17
, and controls the operation of the backward pulse delay circuit
16
based on the information stored in the state-hold circuit
17
in such a manner that the transmission time of the backward pulse signal is equal to the transmission time of the forward pulse. Specifically, all the state-hold circuits
17
in the state-hold section
18
are initially reset. Those state-hold circuits
17
corresponding to the delay circuits
13
in the forward pulse delay circuit
14
to which the forward pulse signal is not transmitted remain reset as in their initial state.
The state-hold circuits
17
corresponding to the delay circuits
13
in the forward pulse delay circuit
14
to which the forward pulse signal is transmitted, on the other hand, are turned to set state. The control signal generated in accordance with the set/reset state of each state-hold circuit
17
is input to the backward pulse delay circuit
16
.
The delay circuits
15
in the backward pulse delay circuit
16
controlled by the control signal from the state-hold circuit
17
corresponding to the set state output the backward pulse signal transmitted from the delay circuit
15
in the succeeding stage to the delay circuit
15
in the preceding stage.
The delay circuit
15
in the backward pulse delay circuit
16
controlled by the control signal from the state-hold circuit
17
corresponding to the reset state, on the other hand, outputs the pulse signal CLK output from the receiver
11
to the delay circuit
15
in the preceding stage.
When the control signal P changes to “H” level, the pulse signal CLK also changes to “H”, and therefore the delay circuits
15
((N+1)th and subsequent stages in
FIG. 1
) in the backward pulse delay circuit
16
controlled by the control signal from the state-hold circuit
17
in reset state are supplied with the “H” pulse signals CLK in parallel.
As shown in
FIG. 1
, assuming that there are N stages of the delay circuits
13
in the forward pulse delay circuit
14
through which the forward pulse signal is transmitted, the state-hold circuits
17
in the first to Nth stages of the state-hold section
18
are in

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