Clock control circuit and semiconductor memory device...

Details Clock control circuit and semiconductor memory device... Clock control circuit and semiconductor memory device...

2007-07-10

2007-07-10

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230080, C365S233500

Reexamination Certificate

active

11319550

ABSTRACT:
The present invention relates to a clock control circuit that can reduce power consumption in the input operation of an address signal and control signals and semiconductor memory device including the same, and an input operation method of the semiconductor memory device. The clock control circuit accordance to the present invention generates a control clock signal only when external address signals or external control signals are substantially input. Therefore, unnecessary power consumption a power noise phenomenon can be reduced.

REFERENCES:
patent: 6809989 (2004-10-01), Takahashi et al.
patent: 6977865 (2005-12-01), Jeong
patent: 1020020018944 (2002-03-01), None

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