Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2001-04-26
2003-02-25
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S292000, C327S295000
Reexamination Certificate
active
06525588
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a clock controlling circuit and a clock controlling method. More particularly, it relates to a clock controlling circuit and a clock controlling method usable with advantage in a clock supplying circuit of a semiconductor integrated circuit having a circuit synchronized with system clocks.
BACKGROUND OF THE INVENTION
In a semiconductor integrated circuit controlling the internal circuit in synchronism with system clocks, preset circuit operations are executed each clock period to control the internal circuit in its entirety. Recently, the chip size is increased in keeping pace with the tendency towards the increasing degree of integration and towards the higher function of the function of the semiconductor integrated circuit. On the other hand, as the clock period becomes shorter with the increasing operating frequency, the shortening of the delay time difference in the clock path is presenting problems.
In order to cope with this task, there is disclosed in, for example, the JP Patent Kokai JP-A-9-258841 a clock supplying method in which there are provided an oncoming clock line and an outgoing clock line, these clock lines are divided into two lines of forward and return paths, and in which the wiring delay is detected to adjust clocks. There is disclosed a configuration comprising a receiver having first and second input terminals at a first position on the forward path and a second position near the first position on the forward path, respectively. The delay in the forward path and return path is detected from these first and second input terminals to output an average value of the delay caused in the forward and return paths.
That is, in the JP Patent Kokai JP-A-9-258841, a point A of a forward route
111
, as an input, is coupled to an end of a phase detection circuit
181
through a variable delay line
171
and a variable delay line
172
, a point H of a return route
112
, as an input, is coupled to the other end of the phase detection circuit
181
, the delay time of the variable delay lines
171
,
172
is variably controlled for phase adjustment, and an output of a receiver is derived from a junction point of the variable delay lines
171
,
172
.
Since the delay time from the point A of the forward route
111
of the clock propagation path up to a turning point
113
is a, the delay time from the point A to the point H is 2a, an average value of the delay time between the points A and H is a, the delay time from the point b of the forward route
111
of the clock transmitting line to the turning point
113
is b and the delay time from the point B to the point G is 2b. So, the sum of the delay time (a−b) from the input end to the point b and the delay time ((a−b)+(a−b)+2b) from the input end to the point G is {(a−b)+((a−b)+(a−b)+2b)) is 2a, with an average value being a. In this manner, clock signals with the corresponding phase can be obtained without dependency on the positions of the clock propagation path.
In this manner, in the conventional method disclosed in the JP Patent Kokai JP-A-9-258841, a clock path is direction-reversed and a delay timing of an intermediate point between the forward and return routes is taken to adjust the delay amount of the variable delay line in the clock path.
For adjusting the delay in this manner, a feedback circuit loop, exemplified by a phase locked loop (PLL) or a delay lock loop (DLL), in which the phase difference is detected by a phase detection circuit and the delay caused in the variable delay line is varied based on the detected phase difference, is routinely used.
SUMMARY OF THE DISCLOSURE
However, the PLL or DLL, constituting a feedback circuit, presents a problem that a period longer by about hundreds to thousands of cycles is needed until clock stabilization is achieved.
There is also raised a problem that plural sets of the phase comparators and delay circuit lines are needed thus increasing the circuit scale.
In view of the aforementioned problems, it is an object of the present invention to provide a clock controlling circuit and a clock control method for a circuit for eliminating the delay difference in the entire clock transmitting line, according to which the delay difference may be eliminated in a shorter time than the case where the PLL circuit or the DLL circuit is used.
It is another object of the present invention to provide a clock controlling circuit and a clock control method according to which a phase comparator may be eliminated to prevent the circuit scale from increasing.
According to a first aspect of the present invention, there is provided a clock controlling circuit comprising:
a timing difference dividing circuit for receiving a clock at a first position on a forward route of a clock propagation path direction-reversing input clocks fed at one end thereof, and a clock at a second position on a return route thereof corresponding to the first position on the forward route,
the timing difference dividing circuit outputting a signal of a delay time corresponding to a time obtained on dividing a timing difference of the two clocks by a preset interior division ratio.
According to a second aspect of the present invention, there is provided a clock controlling circuit comprising:
a timing difference averaging circuit for receiving a clock at a first position on a forward route of a clock propagation path direction-reversing input clocks fed at one end thereof, and a clock at a second position on a return route thereof corresponding to the first position on the forward route,
the timing difference dividing circuit outputting a signal of a delay time corresponding to a time obtained on evenly dividing a timing difference of the two clocks.
According to a third aspect of the present invention, the timing averaging circuit is configured to issue an output signal with a delay time equal to the sum of a first delay time until output signal is issued after one of the two input clocks undergoing transition at an earlier time point is input simultaneously to first and second inputs adapted for being fed with the two clocks and a second delay time corresponding to a time (T/2) obtained on dividing the timing difference T of said two clocks into two equal portions.
According to a fourth aspect of the present invention, there is provided a timing averaging circuit fed with clocks from a first position on a forward route of a clock propagation path, adapted for direction-reversing clocks frequency divided by a frequency dividing circuit and input at an end of the clock propagation path and from a second position on a return route thereof corresponding to the first position on the forward route, and a multiplication circuit for multiplying an output of the timing averaging circuit.
According to a fifth aspect of the present invention, there is provided a clock controlling circuit comprising:
a timing averaging circuit provided with a frequency dividing function for frequency dividing two, first and second, clocks, i.e., the first clock from a first position on a forward route of a clock propagation path fed with input clocks at one end and direction-reversing the input clocks and the second clock from a second position corresponding to the first position to generate frequency divided multi-phase clocks of plural different phases,
the timing averaging circuit outputting a signal of a delay time corresponding to a time equally dividing a timing difference between frequency divided clocks having a corresponding phase among clock signals obtained on frequency division of the two clocks; and
a synthesis circuit for synthesizing plural outputs of the timing averaging circuits into one signal and for outputting the one signal.
According to a sixth aspect of the present invention, there is provided a clock controlling method, averages the timing difference of clocks taken from a first position on a forward route of a clock propagation path fed with input clocks at one end and direction-reversing the input
LandOfFree
Clock control circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock control circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock control circuit and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3139931