Clock control circuit and clock control method

Details Clock control circuit and clock control method Clock control circuit and clock control method

2001-03-23

2002-04-30

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S116000, C327S120000

Reexamination Certificate

active

06380774

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to clock control technology and, more particularly, to a clock control circuit and method using an interpolator for frequency multiplication.
BACKGROUND OF THE INVENTION
In order to deal with an increase in the scale of circuitry that can be integrated on a single chip and in order to handle higher operating frequencies, semiconductor integrated circuits which include a synchronizing circuit that operates upon being supplied with a clock are provided with a clock control circuit for controlling phase and frequency of clocks externally and internally of the chip.
A PLL (Phase-Locked Loop) or a DLL (Delay-Locked Loop) is used conventionally as such a clock control circuit. In semiconductor circuits having system-scale circuitry on a single chip such as an LSI chip (referred to also as a “system on silicon”), it is now necessary to provide a clock control circuit for phase and frequency control for each macroblock within the chip, by way of example.
In addition to use of a PLL or DLL as the conventional clock control circuit, as set forth above, it is also known to use a combination of a PLL or DLL and an interpolator.
FIG. 25
is a block diagram illustrating the structure of a clock control circuit, which comprises a combination of a PLL and an interpolator, described in Reference 1 (ISSC 1993 pp. 160-161, Mark Horowitz et al., “PLL Design for a 500 MB/s Interface”). As shown in
FIG. 25
, a PLL
50
outputs multiphase clock signals P
0
to Pn synchronized to an input clock
1
. The multiphase clock signals P
0
to Pn are input to a switch (selector)
20
A. Two mutually adjacent signals (of even and odd phases) selected by the switch
20
A enter an interpolator (a phase interpolator)
30
A, which delivers an output signal OUT obtained by internally dividing the phase difference between these two input signals. The switch
20
A that selects the pair of signals input to the interpolator
30
A comprises an even-phase selector, a shift register for supplying a selection control signal to the even-phase selector, an odd-phase selector and a shift register for supplying a selection control signal to the odd-phase selector.
In the arrangement described in Reference
1
, the interpolator
30
A has an analog structure comprising a differential circuit that receives two inputs. A control circuit
40
A has an FSM (Finite State Machine) circuit for monitoring phase to check which of the two signals is earlier in phase and for outputting a count signal to an up/down counter (not shown), and a DA converter (not shown) for converting the output of the up/down counter to an analog signal. The DA circuit supplies the interpolator
30
A with a current corresponding to the even/odd phase. The PLL
50
comprises a phase comparator circuit, a loop filter, a voltage-controlled oscillator to which the voltage of the loop filter is input as the control voltage, and a frequency divider for frequency dividing the output of the voltage-controlled oscillator and feeding the resultant signal back to an input of the phase comparator circuit.
FIG. 26
is a block diagram illustrating an example of a clock control circuit, which comprises a combination of a DLL and an interpolator, described in Reference 2 (ISSCC 1997 pp. 332-333, S. Sidiropoulos and Mark Horowitz et al., “A semi-digital delay locked loop with unlimited phase shift capability and 0.08-400 MHz operating range”). As shown in
FIG. 26
, a PLL
60
outputs multiphase clock signals P
0
to Pn synchronized to the input clock
1
. The multiphase clock signals P
0
to Pn are input to a switch
20
B. Two mutually adjacent signals enter an interpolator
30
B, which delivers an output signal OUT obtained by internally dividing the phase difference between these two signals. On the basis of the result of detecting a phase difference between the output OUT and a reference clock, a control circuit
40
B exercises control to vary the internal-division ratio of the interpolator
30
B and controls the switching of the switch
20
B. The interpolator
30
B also is implemented by analog circuits.
FIG. 27
is a block diagram showing an arrangement described in Reference 3 (ISSCC 1997 pp. 238-239, Alan Fiedler, “A 1.0625 Gb/s Transceiver with 2×-Oversampling and Transmit Signal Pre-Emphasis”). This arrangement includes a voltage-controlled oscillator (VCO)
70
to which a clock is input for a adjusting the phase of multiphase clock signals, and a control circuit
40
C. Multiphase clock signals Q
0
to Qn are delivered from the output side of the VCO
70
.
SUMMARY OF THE DISCLOSURE
The clock control circuits according to the prior art described above have a number of problems described below.
In the implementation shown in
FIG. 25
using the PLL, phase adjustment requires an extended period of time and jitter is produced by the feedback loop. The jitter causes a large shift in phase, which also occurs when the PLL is unlocked. In the implementations of
FIG. 25 and 27
, phase error occurs owing to a fluctuation in the center frequency of the VCO.
In the implementation shown in
FIG. 26
using the DLL, there are occasions where the clock signal of the final phase of the multiphase clock signals develops a large shift. Loop jitter also occurs.
As shown in (b) of
FIG. 13
, with a DLL or the like, input-clock jitter (jitter−dt, which causes the clock period to become T—dt) appears in the last clock signal of the output clock (the cycle of the fourth clock pulse of a clock whose frequency has been multiplied by four is T/4−d). As a consequence, the influence of jitter is great.
Accordingly, an object of the present invention, in one aspect, is to provide a clock control circuit and method as well as a semiconductor integrated circuit device in which center-frequency fluctuation caused when a PLL is used and jitter due to a feedback loop are eliminated to thereby reduce phase error to a major degree.
Another object of the present invention is to provide a clock control circuit and method whereby multiphase clock signals can be generated in an instant.
According to a first aspect of the present invention, there is provided a clock control circuit comprising:
a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating a plurality of frequency-multiplied clocks, which have phases that differ from one another, from an input clock; and
at least one phase adjusting interpolator, to which are input two clocks from among the plurality of frequency-multiplied clocks of different phases output from the frequency multiplying interpolator, for outputting a signal obtained by internally dividing a phase difference between these two clocks.
According to a second aspect of the invention, there is provided a clock control circuit comprising:
(a) a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating multiphase clocks obtained by frequency multiplying an input clock;
(b) a switch, to which the multiphase clocks output from the frequency multiplying interpolator are input, for selectively outputting at least a pair of clocks from among the multiphase clocks;
(c) at least one phase adjusting interpolator, to which the pair of clocks output from the switch is input, for outputting a signal obtained by internally dividing a phase difference between the pair of clocks; and
(d) a control circuit for controlling a setting of an internal-division ratio of the phase adjusting interpolator and switching of a clock output by the switch.
According to a third aspect of the present invention, there is provided a clock control circuit comprising:
(a) a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generati

Affiliated with

Also associated with

Rating

Clock control circuit and clock control method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock control circuit and clock control method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock control circuit and clock control method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2828839