Clock control circuit

Details Clock control circuit Clock control circuit

2000-03-30

2003-03-04

Kinkead, Arnold (Department: 2817)

Oscillators

Plural oscillators

Selectively connected to common output or oscillator...

C331S074000, C331SDIG002, C327S144000, C327S147000, C327S150000

Reexamination Certificate

active

06529083

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a clock control circuit in a microcontroller.
BACKGROUND OF THE INVENTION
In recent years, requirements for power conditions in portable telephone or other portable equipment have been becoming more and more strict. In association with this tendency, also the requirement for lower power consumption in an incorporated microcontroller for controlling the portable equipment or the like has been becoming increasingly strong. At the same time, contents of control provided from or the processing executed by the microcontroller has been becoming more and more complicated. To satisfy the requirements described above, it is necessary to see that the microcontroller works at a higher speed, but in this case power consumption per unit time increases.
Therefore, complicated control over the operating speed is performed. In other words, the microcontroller is operated at a higher speed during a period of time when or for sections in which the high processing capability is required, and operated at a lower speed during a period of time when or for sections in which the high processing capability is not required.
In order to change the operating speed of a microcontroller, generally the frequency of the operating clock must be changed. The frequency is generally changed by a multiplication factor in a PLL (phase-locked Loop) oscillation circuit, or by changing a frequency division ratio in a frequency divider circuit. The PLL oscillation circuit is mainly used for the generation of a single operation clock with a higher frequency from a low original oscillation clock. The frequency divider circuit is mainly used for the generation of the operation clock with a lower frequency from a low original oscillation frequency. Further, the frequency divider circuit is also used for the generation of a plurality of frequency-divided clocks so that the frequency can be changed according to a section to be operated for the purpose to reduce a ratio of portions operating at a high frequency.
To provide controls over operation clock with a PLL oscillation circuit or a frequency divider circuit, it is required to discretely control each function unit or set contents. In other words, it is necessary to set a complicated program. For instance, when a multiplication factor in a PLL oscillation circuit is to be changed, at first the clock source is switched to other clock so that the PLL output clock is not used, and then a multiplication factor setting is changed. No operation is performed until the oscillation because of the changed multiplication factor is stabilized. Once the oscillation is stabilized, the clock source is again switched to the PLL output clock.
Further, it is necessary to set a ratio for dividing a clock frequency to an optimal value according to a multiplication factor in the PLL oscillation circuit. For instance, in a case of a circuit for executing communications or the like, at first an operation frequency is fixed at a constant level. When the operation frequency of a CPU (central processing unit) is changed to a higher or lower value, it is required to change the setting of not only the multiplication factor, but also the frequency division ratio. All of these operations are discretely and successively executed by a program.
As described above, control over the operation clock is very complicated. Accordingly, the program structure becomes complicated and the program size also increases. Further, a time required for changing the setting of the multiplication factor or the frequency division ratio becomes disadvantageously longer. Further, precise control over the operation speed can not be provided due to generation of mistakes in setting or due to malfunctions. This disadvantageously increases power consumption.
When the multiplication factor in the PLL oscillation circuit is set at a high value to generate a high frequency and only a frequency division ratio for the used clock frequency, it is possible to reduce the complication in the setting work. With this system, however, it is impossible to reduce the power consumption in the PLL oscillation circuit and in the frequency divider circuit.
SUMMARY OF THE INVENTION
This invention is achieved in view of the problems explained above. It is an object of this invention to provide a clock control circuit which can reduce the complication in control over the operation clock and also which can easily realize precise control over the operation speed.
To achieve the object described above, according to one aspect of the present invention, when it is detected that the PLL output clock output from an PLL oscillation circuit is unstable, a clock state controller provides a series of controls (1) to (4) described below. (1) Output of clock to the outside is stopped. (2) The clock is switched from the PLL output clock to an another clock. (3) After the PLL output clock is stabilized, the clock is switched back to the PLL output clock. (4) Clock generated based on the PLL output clock is output to the outside.
Further, a multiplication factor supplied from a multiplication factor setting unit is once stored in a buffer unit, and the multiplication factor setting data stored in the buffer unit is output to a frequency divider circuit for the generation of feed-back clock.
According to another aspect of the present invention, when setting of a multiplication factor in the PLL oscillator is changed by the multiplication factor setting unit, as multiplication factor setting data output from the multiplication factor setting unit is different from the current multiplication factor setting data output from the buffer unit, so that a series of controls (1) to (5) described below are executed. (1) Output of clock to the outside is stopped. (2) The clock is switched from the PLL output clock to an another clock. (3) The multiplication factor setting data output from the buffer unit is made coincident to those output to the multiplication factor setting unit. (4) After the PLL output clock is stabilized, the clock is switched to the PLL output clock. (5) Clock generated based on the PLL output clock is output to the outside.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 5142247 (1992-08-01), Lada, Jr. et al.
patent: 5903748 (1999-05-01), McCollough et al.

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