Clock control circuit

Details Clock control circuit Clock control circuit

1999-02-03

2002-05-14

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S284000, C327S297000, C327S269000, C365S233500

Reexamination Certificate

active

06388484

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock control circuit suitable for a system which requires an internal clock having a constant delay relation to an external clock in an integrated circuit.
2. Related Art Statement
Recently, a computer system sometimes adopts a synchronous memory, such as a synchronous DRAM, in order to fulfill the requirements for faster processing. A memory of a synchronous type is also designed to use a clock, which is synchronized to the system clock of a computer system within the memory.
When a delay occurs between a clock used within a memory (hereinafter referred to as internal clock) and an external clock, such as a system clock, and particularly when the operating speed is high, malfunction is apt to occur in a circuit even when the delay time is small.
Accordingly, a clock control circuit is adopted to synchronize an internal clock signal to an external clock signal.
FIG. 1
is a circuit diagram showing a related art on such a clock control circuit. A brief description will be given on the theory with reference to the waveform diagrams in
FIGS. 1 and 2
.
In
FIG. 1
, an external clock signal CK, shown in
FIG. 2
, is inputted to an input terminal
1
. This external clock signal CK is taken in through a receiver
2
. The receiver
2
outputs an amplified clock signal CLK after waveform shaping of the external clock signal. When a delay time at the receiver
2
is D
1
, the output clock signal CLK of the receiver
2
turns out to be as shown in
FIG. 2. A
period of the external clock signal CK is supposed to be &tgr;. Without a clock control circuit, as an output signal of the receiver
2
is used as an internal clock signal, the delay time D
1
becomes a synchronization error when synchronization of an external clock signal CK is shortened. In contrast to this, a clock control circuit
9
is designed to generate signals delayed to an external clock signal by two periods of the external clock period by delaying the output clock signal CLK of the receiver
2
by the time (2&tgr;−D
1
).
That is, a clock control circuit
9
, as shown in
FIG. 2
, first generates pulse FCL which rises after the time A from the rising timing of the output clock signal CLK of the receiver
2
. The time from the rising of this pulse FCL to the rising of the next clock signal CLK is, as shown in
FIG. 2
, the time (&tgr;−A). The clock control circuit
9
finds the same time (&tgr;−A) as the time (&tgr;−A), and generates a rearward pulse RCL, shown in
FIG. 2
, after the time 2(&tgr;−A) from the rising of pulse FCL. The rearward pulse RCL is amplified by an output buffer
6
to be able to drive an internal circuit, and outputted as an internal clock signal CK′.
As shown in
FIG. 2
, the time from the rising of the clock signal CLK to the rising of the next pulse RCL is &tgr;−(&tgr;−A)=A. A delay time of the output buffer
6
is supposed to be D
2
. Consequently, as shown in FIG.
2
, the clock signal CLK, which has been delayed by the receiver
2
by the time D
1
to the external clock signal CK is outputted after being further delayed by the time A by a delay monitor
3
, by the time 2(&tgr;−A) by forward-pulse and rearward-pulse delay lines
4
and
5
, and by the time D
2
by the output buffer
6
.
Consequently, a delay of an internal clock signal to an external clock signal becomes 2&tgr;, and the internal clock signal and the external clock signal are synchronized.
This circuit requires a pulse having an external clock signal whose pulse width is narrower than A. When a period of an external clock signal becomes small and A correspondingly becomes small, pulse must be generated to have narrower width, and operation in high frequency becomes difficult.
Hereinafter, configuration, operation and problem of circuits of the related art will be described in detail.
First, description will be given on function and configuration of each part. As a delay time given by the receiver
2
and the output buffer
6
can be found beforehand, it is possible to prepare the delay monitor
3
having a delay time A to be A=D
1
+D
2
, as shown in FIG.
2
.
In
FIG. 1
, the delay monitor
3
is a device to obtain this delay time A. The delay monitor
3
is designed to generate forward pulse FCL, which is the clock signal CLK from the receiver
2
delayed by the delay time A, and to output it to a forward-pulse delay line
4
. The delay time A is set to a value larger than the pulse width of the clock signal CLK. The forward-pulse delay line
4
is for obtaining a delay time (&tgr;−A), and a rearward-pulse delay line
5
is also for obtaining a delay time (&tgr;−A). As is described later it is designed so that rearward pulse RCL, the output of the rearward-pulse delay line
5
, is one delayed by D
1
+A+2(&tgr;−A) to the external clock signal and further delayed by the time D
2
by the output buffer
6
to be outputted as an internal clock signal CK′.
That is, the external clock signal CK inputted through the input terminal
1
is outputted from the output buffer
6
, being delayed by D
1
+A+2(&tgr;−A)+D
2
. When the delay time A of the delay monitor
3
is set to D
1
+D
2
, an internal clock signal CK′, which is synchronized by being delayed by 2&tgr; to the external clock signal CK, is obtained from the output buffer
6
.
The forward-pulse delay line
4
is composed of a plurality of cascaded forward-pulse delay circuits
4
-
1
,
4
-
2
, . . . Each of the forward-pulse delay circuits
4
-
1
,
4
-
2
, . . . is configured with an AND circuit of a NAND circuit and an inverter. To an input terminal of each of the forward-pulse delay circuits
4
-
2
,
4
-
3
, . . . , the output of the forward-pulse delay circuits
4
-
1
,
4
-
2
, . . . in the preceding stage is supplied respectively.
The rearward-pulse delay line
5
is composed of a plurality of cascaded rearward-pulse delay circuits
5
-
1
,
5
-
2
, . . . Each of the rearward-pulse delay circuits
5
-
1
,
5
-
2
, . . . is configured with an AND circuit of a NAND circuit and an inverter. To an input terminal of each of the rearward-pulse delay circuits
5
-
1
,
5
-
2
, . . . , the output of the rearward-pulse delay circuits
5
-
2
,
5
-
3
, . . . in the succeeding stage is supplied respectively. Each of the forward-pulse delay circuits
4
-
1
,
4
-
2
, . . . and each of the rearward-pulse delay circuits
5
-
1
,
5
-
2
, . . . are designed to operate with the same delay time respectively.
Output terminals of the forward-pulse delay circuits
4
-
1
,
4
-
2
, . . . are respectively connected to one input terminal of each of control circuits
7
-
1
,
7
-
2
, . . . , each of which forms a control circuit group
7
. The control circuits
7
-
1
,
7
-
2
, . . . are configured with NAND circuits, and the clock signal CLK from the receiver
2
is supplied to the other input terminals of the control circuits
1
-
1
,
7
-
2
, . . .
The control circuits
7
-
1
,
7
-
2
, . . . are designed to supply two-input NAND output as control signals not only to the other input terminals of the forward-pulse delay circuits
4
-
3
,
4
-
4
, . . . , but also to the other input terminals of the rearward-pulse delay circuits
5
-
1
,
5
-
2
, . . . To the other input terminals of the forward-pulse delay circuits
4
-
1
,
4
-
2
, . . . in a first and second stages, electric potential at high level corresponding to logical value “1” (hereinafter referred to as “H”) is applied. It is also designed so that, to the other input terminals of the rearward-pulse delay circuits in the last stage, signals of “H” are supplied. Output terminals of the rearward-pulse delay circuit
5
-
1
in the first stage are connected to the output buffer
6
. The output buffer
6
is designed to delay the output of the rearward-pulse delay circuit
5
-
1
by the delay time D
2
and to output it as the internal clock signal CK′.
A delay unit
8
is configured with a forward-pulse delay

Affiliated with

Also associated with

Rating

Clock control circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock control circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock control circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2823142