Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1999-08-17
2001-05-08
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S048000, C327S117000
Reexamination Certificate
active
06229369
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a clock control circuit for generating operation clock signals, particularly, to a clock control circuit comprising semiconductor integrated circuits.
2. Description of the Related Art
A semiconductor integrated circuit such as a microcomputer incorporates therein a central processing unit (hereinafter referred to as CPU), an internal circuit as a peripheral circuit of the CPU (hereinafter referred to as a peripheral circuit or as an internal circuit), such as a memory, a timer circuit, an interface circuit or the like. The CPU and the peripheral circuit respectively perform intended functions in response to operation clock signals, each having a given clock period rate which is determined by a frequency.
The need for low power consumption of a semiconductor integrated circuit has recently increased. There is a proposal for supplying operation clock signals having a given clock period determined in response to operation conditions to a CPU or a peripheral circuit as one of the methods of realizing low power consumption.
That is, as for a host unit using a semiconductor integrated circuit, in a state where the semiconductor integrated circuit does not require a processing operation such as a latency, namely, at the time until an instruction for instructing new processing is issued, and the like, the semiconductor integrated circuit is operated in response to operation clock signals of low frequency. In a state where processing is needed in a semiconductor integrated circuit, the semiconductor integrated circuit is operated in response to operation clock signals of a high frequency, which is higher than the operation clock signals of a low frequency. When the semiconductor integrated circuit is operated at low speed in response to the operation clock signals of low frequency, power consumption generated in the semiconductor integrated circuit is reduced by the reduction of the number of operations. Accordingly, it is possible to reduce the waste power consumption in the semiconductor integrated circuit. The control of the operation clock signals is generally performed by software.
The control of operation clock signals set forth above is particularly effective for portable equipment employing a battery which has been recently developed in practical use.
As a peripheral circuit, there are a timer circuit for counting time as mentioned above, an interface circuit for sending and receiving data while communicating with external equipment, and the like. When the peripheral circuit is operated in response to operation clock signals of low frequency for realizing low power consumption, the peripheral circuit incurs delays in operating speed. As a result, for example, a timer circuit normally can not count time. Further, the interface circuit normally cannot send and receive data because of nonconformity with a transmission speed relative to external equipment of the other communication party. If such a drawback is caused by software, the control thereof becomes complex.
Further, as for a frequency adapted for operation clock signals of low frequency in order to efficiently realize low power consumption it is preferable for, the operation clock signals to have an optimum frequency even in the case of operation of the CPU and internal circuit at low speed.
It is an object of the invention to provide a clock control circuit capable of realizing low power consumption without impairing functions of respective circuits constituting a semiconductor integrated circuit.
It is another object of the invention to provide a clock control circuit capable of supplying operation clock signals having an optimum frequency even in the case of operation of a CPU or internal circuit at low speed.
SUMMARY OF THE INVENTION
To solve the above-mentioned problems, the invention comprises a clock control circuit for supplying operation clock signals, each having a given period, to a central processing unit and an internal circuit comprising a divider for generating a divided clock signal which is obtained by dividing a reference clock signal, a first selector for selectively outputting the reference clock signal and the divided clock signal as the operation clock signal relative to the central processing unit, and a second selector for selectively outputting the reference clock signal and the divided clock signal as the operation clock signal relative to the internal circuit.
Further, the clock control circuit of the invention may be structured so that the divider generates a plurality of divided clock signals having different frequencies, and the first and second selectors output either the reference clock signal or one of the plurality of divided clock signals as the operation clock signals.
Further, the clock control circuit of the invention may be structured so that the divider comprises a first subdivider for generating the divided clock signal to be inputted to the first selector and a second subdivider for generating a divided clock signal to be inputted to the second selector.
Further, the clock control circuit of the invention may be structured so that the first subdivider comprises a first counter and includes a first setting circuit for setting an initial-value to the first counter in response to overflow of the first counter, and the second subdivider comprises a second counter and includes a second setting circuit for setting an initial-value to the second counter in response to overflow of the second counter.
Further, the clock control circuit of the invention may comprise a control circuit for controlling switching of outputs of the first and second selectors.
Further, the clock control circuit of the invention may be structured so that switching of the output relative to the first selector is controlled in response to a signal outputted from the internal circuit.
Further, the clock control circuit of the invention may be structured so that the divider comprises counters, and includes setting circuits for setting an initial-value to the counters in response to overflow of the counter.
REFERENCES:
patent: 5666355 (1997-09-01), Huah et al.
patent: 5774702 (1998-06-01), Mitsuishi et al.
Inoue Kazutoshi
Ohie Mitsuya
Yusa Atsushi
Cox Cassandra
Frank Robert J.
Gluck Jeffrey W.
OKI Electric Industry Co., Ltd.
Tran Toan
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