Clock control circuit

Details Clock control circuit Clock control circuit

2002-06-11

2004-08-03

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000, C327S114000

Reexamination Certificate

active

06771100

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock control circuit. More particularly, the invention relates to a clock control circuit capable of achieving desired performance while suppressing power consumption and increase in circuit scale even if there is a signal of a heavy load or a signal having long delay time such as a reset signal.
2. Description of the Background Art
Since a reset signal sets a number of latches at a time, the fan-out is very large. Consequently, it takes time that the reset signal propagates through latches from a reset circuit. Particularly, when the operation frequency is high, it takes time to receive a reset release signal from the outside and release all of latches from the reset state. It becomes a cause of an erroneous operation.
For example, in the case of a circuit shown in
FIG. 20
, a reset signal shown in
FIG. 21B
is supplied to reset terminals (R
1
to R
5
) of D-type flip flops
21
to
25
via a buffer
20
. Since the output of buffer
20
is a load of five D-type flip flops
21
to
25
, there is the possibility that propagation time of reset signal R
1
of D-type flip flop
21
shown in FIG.
21
C and propagation time of reset signal R
5
of D-type flip flop
25
shown in
FIG. 21D
are deviated from each other by one cycle of a clock signal shown in FIG.
21
A. In this case, a reset releasing timing of D-type flip flop
21
to be reset by reset signal R
1
and that of D-type flip flop
25
to be reset by reset signal R
5
are deviated from each other by a clock cycle, and it becomes a cause of an erroneous operation.
Although the maximum frequency of a system is determined by a slowest path, pulse delay of releasing a reset state decreases the operation frequency of an LSI, and the performance of the whole deteriorates.
Methods for solving the problem include a method of connecting buffers
31
to
34
to the output of a buffer
30
in a tree structure as shown in
FIG. 22 and a
method of propagating a reset signal by a buffer
40
of a large output as shown in FIG.
23
. However, the methods have a disadvantage of a large circuit scale and high power consumption.
Other than the reset signal, a similar problem may occur in a signal source having long delay time from which signals are supplied to many blocks.
For example, as shown in
FIG. 24
, in the case of a path extending from A to B including a node of large fan-out such that a number buffers
41
to
46
are connected to the output of buffer
40
, when a delay time from the timing of the rising edge of a signal A shown in
FIG. 25B
to the timing of the rising edge of a signal B shown in
FIG. 25C
becomes longer than a clock cycle shown in
FIG. 25A
, an erroneous operation is caused.
Methods for solving the problems include a method of forming a tree structure and a method of propagating a reset signal by a buffer of a large output in a manner similar to the case of the reset signal. However, the methods have similarly a disadvantage of a large circuit scale and high power consumption.
SUMMARY OF THE INVENTION
An object of the present invention is therefore to provide a clock control circuit which solves the problems by decreasing the frequency of a clock signal or stopping the clock signal after or for a period in which a state of a signal having a long delay time such as a reset signal changes.
The invention relates to, briefly, a technique of stopping supply of a clock signal by a gate circuit in response to a first signal and, when the first signal changes from a first state to a second state, stopping the supply of the clock signal always only for a predetermined period by a gate control circuit.
According to the invention, therefore, after elapse of sufficient time since the first signal has propagated, the clock signal is re-supplied from the output of the gate circuit, so that no erroneous operation occurs. As a result, it is unnecessary to use a buffer of a large output or employ a tree structure for a node having long delay time, and a small circuit of low power consumption can be realized.
Further, according to another aspect of the invention, supply of a clock signal is stopped by a gate circuit in response to a first signal, a second signal of which logic level changes is generated by a gate control circuit in response to the first signal, and the supply of the clock signal is stopped for a period in which the logic level of the second signal changes.
According to further another aspect of the invention, the frequency of a clock signal is decreased by a clock converting circuit in response to a first signal and, when the first signal changes from a first state to a second state, the frequency of the clock signal is decreased always only for a predetermined period by a clock switching circuit.
Further, according to another aspect of the invention, in response to a first signal, a clock signal of which frequency is decreased by a clock converting circuit is output from the clock converting circuit. A second signal of which logic level changes in response to the first signal is generated by a clock switching circuit. The frequency of the clock signal is decreased for a period in which the logic level of the second signal changes.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


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Related U.S. Application Ser. No. 09/476,127, filed Jan. 3, 2000.
Related U.S. Application Ser. No. 09/670,584, filed Sep. 27, 2000.

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