Clock control circuit

Details Clock control circuit Clock control circuit

2002-05-16

2003-06-24

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S151000

Reexamination Certificate

active

06583655

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a clock control circuit and, more particularly, to a clock control circuit that employs an interpolator.
BACKGROUND OF THE INVENTION
A PLL (Phase-Locked Loop) or a DLL (Delay-Locked Loop) is used as a clock control circuit for supplying a clock to a sequential circuit or circuit block driven by a clock. In addition, a combination of a PLL, DLL and interpolator also is known in the art.
Several examples of clock control techniques using interpolators will now be described. The generation of multiphase clocks P
0
to Pn using a PLL circuit is described in Reference 1 (ISSC 1993 pp. 160-161, Mark Horowitz et al., “PLL Design for a 500 MB/s Interface”). In an arrangement described in Reference 1, as shown in
FIG. 16
, a PLL
1510
outputs multiphase clock signals P
0
to Pn synchronized to an input clock
1
. The multiphase clock signals P
0
to Pn are fed to a switch
1520
. Two mutually adjacent signals (of even and odd phases) selected by the switch
1520
are provided to an interpolator (a phase interpolator)
1530
, which produces an output signal OUT obtained by internally dividing the phase difference between these two input signals. The switch
1520
that selects the pair of signals provided to the interpolator
1530
comprises an even-phase selector, a shift register for supplying a selection control signal to the even-phase selector, an odd-phase selector and a shift register for supplying a selection control signal to the odd-phase selector.
In the arrangement described in Reference 1, the interpolator
1530
has an analog structure comprising a differential circuit that receives two inputs. A control circuit
1540
has an FSM (Finite State Machine) circuit for monitoring phase to determine which of the two inputs is earlier in phase and for outputting a count signal to an up/down counter (not shown), and a DA converter (not shown) for converting the output of the up/down counter to an analog signal. The DA converter supplies the interpolator
1530
with a current corresponding to the even/odd phase. The PLL
1520
comprises a phase comparator circuit, a loop filter, a voltage-controlled oscillator (VCO) to which the voltage of the loop filter is input as the control voltage, and a frequency divider for frequency dividing the output of the voltage-controlled oscillator and feeding the resultant signal back to an input of the phase comparator circuit.
Further, Reference 2 (ISSCC 1997 pp. 332-333, S. Sidiropoulos and Mark Horowitz et al., “A semi-digital delay locked loop with unlimited phase shift capability and 0.08-400 MHz operating range”) describes an arrangement in which a DLL (Delay-Locked Loop) circuit is used instead of the PLL circuit of FIG.
16
. Here a DLL outputs multiphase clock signals P
0
to Pn synchronized to the input clock. The multiphase clock signals P
0
to Pn are input to the selector (switch)
1520
. Two mutually adjacent signals enter the interpolator
1520
, which delivers the output signal OUT obtained by internally dividing the phase difference between these two signals. On the basis of the result of detecting a phase difference between the output OUT and a reference clock, the control circuit
1540
conducts control to vary the interior-division ratio of the interpolator
1530
and controls the switching of the selector
1520
. The interpolator also is implemented by analog circuits.
In order to provide a clock control circuit that reduces phase error to a major degree by eliminating center-frequency fluctuation, which is caused when a PLL or the like is used, and jitter that is ascribable to a feedback loop, the Applicant has proposed a clock control circuit, which is described in the specification of Japanese Patent Application No. 2000-083579, that uses a frequency multiplying interpolator as multiphase clock generating circuit for generating the multiphase clock signals P
0
to Pn.
Reference will be had to
FIG. 14
to give an overview of this clock control circuit, which uses an interpolator, proposed in Japanese Patent Application No. 2000-083579 (still undisclosed at the time of filing of this application). Clock signals P
0
to Pn generated using a frequency multiplying interpolator as a multiphase clock generating circuit
210
are adjusted to any phase by a clock selector
170
and a fine adjusting interpolator
130
. As described in the specification of Japanese Patent Application No. 2000-083579, the frequency multiplying interpolator includes a frequency divider for frequency dividing an input clock to thereby generate and output multiphase clocks; a cycle sensing circuit for sensing the cycle of the input clock, and a multiphase-clock frequency multiplying circuit, which has the multiphase clocks output by the frequency divider input thereto, for generating multiphase clocks obtained by frequency multiplying these multiphase clocks. The multiphase-clock frequency multiplying circuit has a plurality of timing-difference dividing circuits each for outputting a signal obtained by dividing a timing difference between two inputs applied thereto, and a plurality of multiplexing circuits each for multiplexing and outputting output signals from two timing-difference dividing circuits. Each of the plurality of timing-difference dividing circuits has a timing-difference dividing circuit (interpolator) to which two identical-phase clocks are applied as inputs and a timing-difference dividing circuit to which two clocks of mutually adjacent phases are applied as inputs. In the present invention, the multiphase clock generating circuit
210
is not limited to a frequency multiplying interpolator; any suitable arrangement may be used. A detailed description of the frequency multiplying interpolator proposed by the aforesaid Japanese Patent Application No. 2000-083579 is not included in the specification of this application.
On the basis of a control signal S (referred to as a “clock selection signal”) output from the control circuit
200
, the clock selector
170
selects mutually adjacent odd- and even-phase signals as a signal pair from the multiphase clock signals P
0
to Pn output by the multiphase clock generating circuit
210
, and supplies these signals to the interpolator
130
.
On the basis of a control signal C and its complementary signal CB output from the control circuit
200
, the interpolator
130
outputs a signal of a propagation delay tpd, which is defined by a time obtained by internally dividing the phase difference (timing difference) between two input signals applied thereto.
The control circuit
200
has a shift register (not shown) as a circuit for supplying the interior-division ratio control signal C/CB to the interpolator
130
. Upon receiving an output signal (the result of a phase comparison) from a phase comparator that compares the phase of a reference clock (not shown) and the phase of the output clock from the interpolator
130
, the control circuit
200
outputs the interior-division ratio control signal C/CB, which is for varying the timing-difference division value (interior-division ratio) of the timing difference between the two inputs to the interpolator
130
, in order to compensate for phase lead/lag in accordance with the degree of phase lead/lag of the output of interpolator
130
with respect to the reference clock. An arrangement may be adopted in which the control signal CB, which is the complement of the interior-division ratio control signal C, is not generated in the control circuit
200
. Rather, a signal obtained by inverting each control signal C, which is output from the control circuit
200
, by an inverter, may be supplied to the interpolator
130
as the signal CB.
Further, the control circuit
200
has a counter and a decoder (neither of which are shown) as the circuit for supplying the clock selection control signal S to the clock selector
170
. If, when it is detected that the setting of the interior-division ratio of the interpolator
130
has reached an upper or lower limit (extremal point), it is necessary to adjust further the l

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