Clock control apparatus and method and image forming...

Incremental printing of symbolic information – Light or beam marking apparatus or processes – Scan of light

Reexamination Certificate

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Reexamination Certificate

active

06512534

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an image forming apparatus which generates image information of, e.g., an electrostatic latent image on an image holding surface of a photosensitive body, electrostatic transfer medium or the like, by introducing optically-modulated laser light from a laser light source, and more particularly, to a clock control apparatus and method and an image forming apparatus using the apparatus preferably applicable to a color image forming apparatus having plural drums for outputting overlapped plural color images.
BACKGROUND OF THE INVENTION
Conventionally, in color image forming apparatuses having plural drums, as a print sheet is conveyed from one of the drums to the next, a positional shift for each color occurs in a main-scanning direction, perpendicular to a paper conveyance direction, which causes color unevenness. To correct such positional shift in the main-scanning direction (hereinafter, simply referred to as “positional correction”), a construction to perform positional correction by 1
pixel (n is an integer) in the main-scanning direction for each color is used.
Hereinafter, a main-scanning direction synchronization control technique related to general positional correction will be described with reference to
FIGS. 7
to
12
.
In
FIG. 7
, reference numeral
601
denotes a main-scanning synchronization detection circuit;
602
, an original clock generation circuit;
603
, a main-scanning synchronizing clock generation unit which inputs a main-scanning synchronizing signal S
601
outputted from the main-scanning synchronization detection circuit
601
and an original clock S
602
outputted from the original clock generation circuit
602
and outputs a pixel clock S
603
synchronized with the main-scanning synchronizing signal S
601
;
604
, a delay unit which delays the pixel clock S
603
outputted from the main-scanning synchronizing clock generation unit
603
by a delay amount (delay by 1
pixel) in accordance with a positional correction amount designation signal S
606
designated from a CPU (not shown);
605
, a PWM generation unit which generates a PWM signal corresponding to a pixel density from a delayed pixel clock S
604
outputted from the delay unit
604
, image data S
607
and a pixel density designation signal S
608
inputted from an image processor (not shown); and
606
, a laser driving unit which drives a laser
607
in accordance with the PWM signal S
605
outputted from the PWM generation unit
605
.
The delay unit
604
has a circuit construction as shown in FIG.
8
. In this example, the pixel delay amount is ¼ pixel. In this figure, numerals
610
to
612
denote delay devices each having a delay amount equal to ¼ of the duration of the pixel clock
5503
. Numeral
613
denotes a selector which inputs four clocks respectively shifted by ¼ clock, i.e., the pixel clock S
603
, a clock S
610
obtained by the delay device
610
by delaying the pixel clock S
603
by ¼, a clock S
511
obtained by the delay device
611
by delaying the clock S
510
by ¼, and a clock S
512
obtained by the delay device
612
by delaying the clock S
611
by ¼, and selects one of the input clocks in accordance with the positional correction amount designation signal S
606
from the CPU (not shown) and outputs the selected clock as the delayed pixel clock S
604
.
In the timing chart of
FIG. 9A
, the clocks S
603
and S
604
have the signal waveforms shown, in a case where the delay devices
610
to
612
are ideal delay devices. Further, the delayed pixel clock S
604
in
FIG. 9A
has the signal waveform shown in a case where a C input of the selector is selected in accordance with the positional correction amount designation signal S
606
from the CPU.
FIG. 10
shows an example of circuit construction of the PWM generation unit
605
which inputs the delayed pixel clock S
604
outputted from the delay unit
604
.
In
FIG. 10
, numeral
620
denotes a D/A converter which D/A-converts the image data S
607
inputted from the image processor (not shown);
621
, a triangular wave generator comprising an integrator and the like, which is driven by the delayed pixel clock S
604
, and which generates a triangular wave in synchronization with the delayed pixel clock S
604
; and
624
, a comparator which compares an analog signal S
620
corresponding to the image data outputted from the D/A converter
620
with a triangular wave S
621
outputted from the triangular wave generator
621
. The triangular wave generator
621
and the comparator
624
together constitute a high-density PWM generator P
1
.
Further, in
FIG. 10
, numeral
622
denotes a divider which {fraction (3/2)}-divides the pixel clock S
604
(i.e., divides the clock by {fraction (3/2)}). The divider
622
has a circuit construction as shown in FIG.
11
.
FIG. 12A
is a timing chart of respective signals in FIG.
11
. The construction and operation of the divider
622
will be described with reference to
FIGS. 11 and 12A
. A double clock S
631
, which is double of the pixel clock S
604
, is generated by exclusive OR logic operation by a logic element
630
between the input delayed pixel clock S
604
and a clock S
630
obtained by the delay device
610
by delaying the pixel clock S
604
by ¼. Then, the double clock S
631
is ⅓ divided by the ⅓-divider
631
, into a {fraction (3/2)} clock S
622
.
Returning to
FIG. 10
, numeral
623
denotes a triangular wave generator comprising an integrator or the like, which is driven by the {fraction (3/2)} clock S
622
outputted from the {fraction (3/2)}-divider
622
, and which generates a triangular wave in synchronization with the {fraction (3/2)} clock S
622
. Numeral
625
denotes a comparator which compares the analog signal S
620
corresponding to the image data outputted from the D/A converter
620
with the triangular wave S
623
outputted from the triangular wave generator
623
. The divider
622
, the triangular wave generator
623
and the comparator
625
together constitute a low-density PWM generator P
2
.
Numeral
626
denotes a selector which inputs PWM waveforms S
624
and S
625
of different periods outputted from the comparator
624
in the high-density PWM generator P
1
and the comparator
625
in the low-density PWM generator P
2
, selects one of the waveforms in accordance with the pixel density designation signal S
608
from the image processor (not shown), and outputs the selected waveform as the PWM signal S
605
.
In a color copying machine, the circuit as described above is provided respectively for yellow, magenta, cyan and black colors. A CPU (not shown) calculates a relative shift amount in the main-scanning direction for each color, and inputs a positional correction amount into the delay unit
604
for each color, thereby correcting the shift by 1
pixel in the main-scanning direction for each color.
However, as the delay devices
610
to
612
used for positional correction are not ideal devices, the actual delay amount at the rising edge and that at the falling edge of pixel clock outputted from the delay device are somewhat different. Consequently, the duty of the clock inputted into the PWM generation unit
605
at the next stage is not 50%. For this reason, in the conventional art, the PWM signal cannot be uniform depending on printing pixel density, and in such case, image quality is seriously degraded. This problem will be described with reference to
FIGS. 9B
,
12
B and
13
. Note that in the following description, the PWM signal is nonuniform when the printing pixel density is low ({fraction (3/2)} frequency division).
As described above, if the delay devices
610
to
612
are ideal devices, delay is effected by an amount of ¼ pixel at the rising edge and the same at the falling edge, as shown in FIG.
9
A. In the figure, the letter T denotes one period of the pixel clock S
603
; and ¼T, ¼ period of one pixel.
However, actually, at the rising edge, delay occurs in an amo

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