Clock combining circuit

Details Clock combining circuit Clock combining circuit

1997-04-17

1999-07-27

Huber, Paul W.

Dynamic information storage or retrieval

Binary pulse train information signal

Binary signal gain processing

369 60, 360 51, G11B 576, G11B 509

Patent

active

059302160

ABSTRACT:
A clock combining circuit includes a FIFO circuit, a signal combining circuit and a signal selecting circuit. The FIFO circuit accepts, for example, a positive-edge playback signal RDATA0 that has as data the positive edge of a playback signal obtained from recording domains formed in a recording medium, RDATA0 being synchronized with a positive-edge clock signal RCLK0. The FIFO circuit also accepts a negative-edge playback signal RDATA1 that has as data the negative edge of the playback signal, RDATA1 being synchronized with a negative-edge clock signal RCLK1. The FIFO circuit causes RDATA0 and RDATA1 to be synchronized with RCLK0 so as to output a delayed positive-edge playback signal RDATA0D and a delayed negative-edge playback signal RDATA1D. The delayed negative-edge playback signal is delayed by -KT to +LT, where K and L are integers and T is the clock period. The signal combining circuit combines the delayed positive-edge and negative-edge playback signals, and outputs (K+L+1) combined signals. The signal selecting circuit detects marks contained in the playback signal, the marks being independent of the (K+L+1) combined signals, and outputs selected ones of the combined signals based on the detected marks.

REFERENCES:
patent: 5235590 (1993-08-01), Taguchi et al.
patent: 5726966 (1998-03-01), Sugaya
patent: 5745468 (1998-04-01), Nakano

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