Clock clamping circuit that prevents clock glitching and method

Details Clock clamping circuit that prevents clock glitching and method Clock clamping circuit that prevents clock glitching and method

1996-08-05

1998-09-15

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By presence or absence pulse detection

327 18, 327 23, 327142, H03K 5156

Patent

active

058084851

ABSTRACT:
A system for clamping a clock signal line that prevents clock glitching is disclosed. The system is comprised of a plurality of logic gates which generates a signal to clamp the clock signal line only on the occurrence of the clock signal line being low, a clock clamping signal 26 is generated indicating that a peripheral device wants to clamp the clock signal line, and a start condition is detected indicating that the clock signal line may be clamped.

REFERENCES:
patent: 4362957 (1982-12-01), Stern
patent: 4374361 (1983-02-01), Holden
patent: 5161175 (1992-11-01), Parker et al.

Affiliated with

Also associated with

Rating

Clock clamping circuit that prevents clock glitching and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock clamping circuit that prevents clock glitching and method , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock clamping circuit that prevents clock glitching and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-92231