Clock circuitry for DDR-SDRAM memory controller

Details Clock circuitry for DDR-SDRAM memory controller Clock circuitry for DDR-SDRAM memory controller

2007-01-30

2008-09-09

Mai, Son L (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S233130

Reexamination Certificate

active

07423928

ABSTRACT:
A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2X clock signal.

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