Clock circuit with self correcting duty cycle

Details Clock circuit with self correcting duty cycle Clock circuit with self correcting duty cycle

2001-08-01

2003-02-11

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S108000, C327S291000, C327S363000, C331S040000

Reexamination Certificate

active

06518809

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for the generation of clock signals, and more particularly, to a method and/or architecture for correcting the duty cycle of an output clock signal.
BACKGROUND OF THE INVENTION
Digital electronic circuits and systems rely on clock signals to ensure correct operation. A clock signal transitions from a low voltage potential to a high voltage potential and remains at the high voltage potential for a fixed period of time. The clock signal then transitions to the low voltage potential and remains at the low voltage potential for another fixed period of time. One cycle of high time and low time forms a complete clock cycle. The duty cycle of a clock signal is defined as the ratio of the high time versus the total period (i.e., total period=high time+low time) during a clock cycle. Typically, clock signals have a target duty cycle of 50% (i.e., the high period and the low period should be equal in duration).
In PLL based clock chips, the duty cycle will be degraded at the higher end of the frequency range since there are no dividers between VCO outputs and driver inputs. Therefore, the VCO duty cycle (typically between 49% to 51%) is passed to the drivers. Additionally, the driver will introduce 2-3% duty cycle degradation. The output clock signal will have duty cycle variation of 46% to 54% or even higher.
Referring to
FIG. 1
, a duty cycle correction circuit
10
based on programming adjustment values in an on-chip memory is shown. The clock signal CLOCK_INPUT is typically a clock signal having a desirable frequency for the clock output signal PRE-DRIVER_OUTPUT. The clock signal CLOCK_INPUT will have a duty cycle close to 50%. However, for higher speed clock frequencies, generation of an accurate duty cycle is difficult. In high frequency implementations, the clock signal CLOCK_INPUT is generated by a phase locked loop (PLL) that has a variable duty cycle (i.e., 45% to 55%). The transistors MP
1
, MN
1
, MP
3
and MN
2
are driven by the clock signal CLOCK_INPUT, while the transistors MP
2
and MN
3
are each driven by a separate value stored in the memory (i.e., EPROM bit P and EPROM bit N). The on-chip memory is typically an electronically programmable read only memory (EPROM).
The EPROM duty cycle correction circuit
10
has substantial costs. The circuitry required to write, read and perhaps latch the EPROM bit values P and N can occupy considerable chip area. The circuitry also adds considerable complexity, design and debug considerations. Furthermore, individually testing and programming of the circuit
10
requires considerable time and cost during the manufacturing process.
Referring to
FIG. 2
, a duty cycle correction circuit
20
based on programming adjustment values in metal mask operations is shown. The clock signal CLOCK_INPUT drives the gates of PMOS type pull up transistor MP
1
and (optionally) of the PMOS type pull up transistor MP
2
. The clock signal CLOCK_INPUT also drives the gates of the NMOS type pull down transistor MN
1
and of (optionally) the NMOS type pull down transistor MN
2
. The adjusted clock signal PRE_DRIVER_OUTPUT results from the pull up action of transistor MP
1
(and of the transistor MP
2
if the metal mask programming option is selected) working against the pull down action of transistor MN
1
(and of the transistor MN
2
if the metal mask programming option is selected). The circuit
20
provides three correction options (i) no duty cycle correction, (ii) one step of positive duty cycle correction and (iii) one step of negative duty cycle correction. Since the duty cycle adjustment of the circuit
20
is applied at fabrication, each Integrated Circuit (IC) requires the same correction to be applied during fabrication.
The typical duty cycle correction circuits
10
and
20
have drawbacks. For example, the threshold adjust of the pre-driver is done by adding extra legs in the pullup or pulldown path using EPROM bits or metal masks. Therefore, the duty correction circuits
10
and
20
do not address duty cycle degradation due to process spread.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a driver and an adjustment circuit. The driver circuit may be configured to generate an output signal in response to a clock input signal and an adjustment signal. The adjustment circuit may be configured to generate the adjustment signal in response to the output signal. The adjustment signal may be configured to correct a duty cycle of the output signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for correcting a duty cycle of a system clock signal that may (i) provide self-correcting duty cycle adjustment, (ii) provide an on-chip implementation, (iii) minimize duty cycle variations due to process spread, (iv) control a tunable pre-driver circuit, (v) reduce testing time, (vi) not require a non-volatile memory, thereby reducing cost and/or (vii) sense an output duty cycle of a driver to provide correction.


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