Clock circuit having a swept output frequency

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307271, 328 46, 364703, H03B 2300

Patent

active

042176557

ABSTRACT:
Disclosed is a digital circuit for generating a swept clock frequency having a linear rate of change. A constant frequency signal is divided by a counter signal representative of the inverse of a linearly changing time dependent variable. The value of the counter signal is varied at the proper rate by means of a pair of rate multipliers and a frequency divider. Included are means for controlling the slope of the output frequency.

REFERENCES:
patent: 3621403 (1971-11-01), Seiy
patent: 3633017 (1972-01-01), Crooke et al.
patent: 3739374 (1973-06-01), Kiowski
patent: 3840814 (1974-10-01), Schiffman
patent: 3870963 (1975-03-01), Groce et al.
patent: 4075544 (1978-02-01), Leenhouts

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