Clock circuit having a clocked output buffer

Details Clock circuit having a clocked output buffer Clock circuit having a clocked output buffer

1989-04-10

1990-05-29

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307475, 307481, 307269, H03K 19096

Patent

active

049298542

ABSTRACT:
A semiconductor integrated circuit device includes an internal logic circuit for carrying out a logic operation and generating an output signal based on the logic operation, and an output buffer circuit connected to the internal logic circuit, for outputting the output signal through an output terminal in synchronism with a clock signal. The semiconductor integrated circuit also includes a non-overlap clock generator, and a third-clock generator. The non-overlap clock generator generates a first internal clock signal which falls in synchronism with a falling edge of an external clock signal, and generates a second internal clock signal which falls in synchronism with a rising edge of the external clock signal, the internal logic circuit carrying out the logic operation in synchronism with the first and second internal clock signals. The third-clock generator generates a third internal clock which rises in synchronism with the falling edge of the second internal clock signal and which falls in synchronism with the falling edge of the first internal clock signal, the third internal clock being supplied, as the clock signal, to the output buffer circuit.

REFERENCES:
patent: 4035663 (1977-07-01), Stodola
patent: 4420696 (1983-12-01), Gemma et al.
patent: 4604731 (1986-08-01), Konishi
patent: 4719365 (1988-01-01), Misono
patent: 4751407 (1988-06-01), Powell
patent: 4797573 (1989-01-01), Ishimoto
patent: 4816700 (1989-03-01), Imel
patent: 4843254 (1989-06-01), Motegi et al.
patent: 4866310 (1989-09-01), Ando et al.

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