Clock circuit for generating a high resolution output from a low

Details Clock circuit for generating a high resolution output from a low Clock circuit for generating a high resolution output from a low

1996-09-04

1999-05-11

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327258, 327293, H03K3/00

Patent

active

059031760

ABSTRACT:
A high resolution clock circuit apparatus and a method of generating a high resolution clock output from a lower resolution clock input utilizes conventional technology. A standard clock generates a clock frequency which is divided by a flip-flop circuit and is applied to a low skew differential clock driver which distributes the clock into a plurality of separate outputs, each output is applied to a different length delay line. The output of each delay line is applied to a latching circuit, such as a low power octal ECL/TTL bidirectional translator. Each of the plurality of delay lines is sampled and a time word is latched when a time measurement is to be made. In this event, a control signal toggles from low to high which latches a digital word representing that subnanosecond interval of time. A shift register also receives the input clock frequency and includes a feedback loop and is applied to the latch circuit. The output of the two latches are input into a PROM used to convert the input code into a binary coded decimal.

REFERENCES:
patent: 4847870 (1989-07-01), Butcher
patent: 4989175 (1991-01-01), Boris et al.
patent: 5235699 (1993-08-01), Shaffer et al.
patent: 5247656 (1993-09-01), Kabuo et al.
patent: 5544342 (1996-08-01), Dean

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