Clock circuit for generating a delay

Details Clock circuit for generating a delay Clock circuit for generating a delay

1998-06-25

2001-08-07

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S115000, C327S117000, C327S269000, C327S400000

Reexamination Certificate

active

06271702

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to delay circuits generally and, more particularly, to a circuit and method for generating an output delay in response to a clock.
BACKGROUND OF THE INVIENTION
Delay elements vary with process, voltage and temperature variations. Previous solutions for generating delays require that delays be tested to ensure the desired specification parameters have been met. An example of such a conventional delay generation is shown in the circuit
10
of FIG.
1
. The circuit
10
generally comprises a divide block
12
and a delay line
14
. The divide block
12
has an input
15
that may receive a periodic frequency from a voltage control oscillator (VCO), not shown. The divide block
12
has a first output
16
and a second output
18
. The output
16
generates a clock signal CLK
1
that may be an integer divided clock of the signal receive at the input
15
. The output
18
presents a signal CLK
2
that may be an integer divided clock of the signal received at the input
15
. The delay line
14
delays the signal presented at the output
18
to present a signal CLK
2
. The signal CLK
2
is delayed from the signal CLK
1
by an amount defined by the delay line
14
. The circuit
10
suffers from a variety of problems including variations caused by process, voltage and temperature variations. Additionally, the circuit
10
is difficult to model, may be sensitive to load variations and may introduce jitter. The introduction of jitter is often the result of slow-edge transitions and delay modulation within delay line
14
(i.e., the delay is a function of the voltage (f(V)).
Referring to
FIG. 2
, a circuit
20
illustrates a simplified view of a second conventional approach for delay generation. A circuit
20
comprises a number of delay elements
22
a-
22
n
. A number of outputs (i.e., phase
1
, phase
2
and phaseN) represent internal taps from a VCO. By tapping the VCO ring elements, the overall VCO layout may be complicated, which may be particularly true in a design application where the internal design of the VCO is not convenient to alter. Additionally, by tapping the ring elements of the VCO, each element has an additional load, which may affect the ultimate maximum frequency of oscillation of the VCO. Additionally, it may be difficult to implement synchronous divides from different clock phases of a VCO.
SUMMARY OF THE INVENTION
The present invention concerns a delay generation circuit comprising (i) a circuit configured to generate a reference clock signal having a period, (ii) a divide circuit and (iii) an output circuit. The divide circuit may be configured to generate a first divided clock signal and a second divided clock signal in response to said reference clock signal. The output circuit may be configured to generate (i) a first output clock signal and (ii) a second output clock signal in response to (i) the first and second divided clock signals and (ii) the reference clock signal. The second output clock signal may have a delay with respect to the first output clock signal. The delay may be (i) a multiple of or (ii) a fraction of the period of the reference clock signal.
The objects, features and advantages of the present invention include providing a delay from a known/time invariable frequency that may (i) be simple to implement and (ii) avoid introducing load jitter when compared to a conventional delay.


REFERENCES:
patent: 5365119 (1994-11-01), Kivari

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