Clock circuit

Details Clock circuit Clock circuit

1995-01-04

1996-01-09

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

331 1A, 331 25, 331 60, 331 74, 327155, 327156, 327159, H03L 700, H03L 706

Patent

active

054832047

ABSTRACT:
A clock circuit for supplying an output clock signal to a logic circuit, includes a phase difference-to-voltage converter producing a voltage signal corresponding to a phase difference between a basic clock signal and a feedback clock signal, a voltage-controlled phase controller controlled by the voltage signal from the phase difference-to-voltage converter and outputting a first clock signal, a clock supply circuit receiving the first clock signal, and supplying a second clock signal, as the output clock signal, through to the logic: circuit, a dummy clock circuit having a dummy capacitance circuit, receiving the first clock signal, and outputting a third clock signal, and a selector selectively supplying the phase difference-to-voltage converter, with a selected one of the output of the clock supply circuit and the output of the dummy clock circuit, as the feedback clock signal.

REFERENCES:
patent: 4868522 (1989-09-01), Popat et al.
patent: 5079519 (1992-01-01), Ashby et al.
patent: 5260979 (1993-11-01), Parker et al.
patent: 5294894 (1994-03-01), Gebara
patent: 5307381 (1994-04-01), Ahuja
"Use of a PLL in a 0.5 .mu.m ASIC: Interface Design as a Crux of Speed Increase", Nikkei Micro Devices, Feb. 1993, pp. 81-85 (No author (not translated)).
Mark Horowitz, "Clocking Strategies in High Performance Processors", 1992 Symposium of VLSI Circuits Digest of Technical Papers, pp. 50-53, (no month, 1992).

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