Clock check circuits using delayed signals

Details Clock check circuits using delayed signals Clock check circuits using delayed signals

1979-11-29

1981-10-13

Malzahn, David H.

Excavating

364200, H03K 519, G06F 104

Patent

active

042952204

ABSTRACT:
In a data processing or transmission system which includes at least two synchronized clocks, for example--T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock.
Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.

REFERENCES:
patent: 3602900 (1971-08-01), Viroflay et al.
patent: 3803568 (1974-04-01), Higashide
patent: 3866184 (1975-02-01), Buhrke et al.
patent: 3932847 (1976-01-01), Smith
patent: 4144448 (1979-03-01), Pisciotta
Brown et al, "Checking Digital System Clock Pulses", IBM Tech. Disclosure Bulletin, vol. 11, No. 3, Aug. 1968, pp. 257-258.

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