Clock check circuit

Details Clock check circuit Clock check circuit

1979-12-03

1981-12-29

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307471, H03K 5135, H03K 514, H03K 526

Patent

active

043084729

ABSTRACT:
An apparatus adapted to check for the continuous presence of an incoming clock pulse train comprising an exclusive OR gate, to the input of which are coupled the clock pulse train and a second train of clock pulses delayed by one half the period of the incoming clock pulse train. A third train of clock pulses delayed by three quarters of the clock period is utilized to strobe the OR gate output into a pair of flip-flops. If the two inputs to the OR gate are the same a fault exists and a flip-flop is set to indicate on which excursion the fault occurred.

REFERENCES:
patent: 3114109 (1963-12-01), Melas
patent: 3876951 (1975-04-01), McLean et al.
patent: 4031410 (1977-06-01), Kikuchi

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