Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2008-05-06
2008-05-06
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S159000
Reexamination Certificate
active
07368965
ABSTRACT:
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.
REFERENCES:
patent: 4805021 (1989-02-01), Harlos et al.
patent: 5910740 (1999-06-01), Underwood
patent: 6198690 (2001-03-01), Kato et al.
patent: 6208183 (2001-03-01), Li et al.
patent: 6292040 (2001-09-01), Iwamoto et al.
patent: 6373913 (2002-04-01), Lee
patent: 6437613 (2002-08-01), Shim et al.
patent: 6556489 (2003-04-01), Gomm et al.
patent: 6586979 (2003-07-01), Gomm et al.
patent: 6727734 (2004-04-01), Gomm
patent: 6727740 (2004-04-01), Kirsch
patent: 6735148 (2004-05-01), Gomm
patent: 6737897 (2004-05-01), Gomm et al.
patent: 6759882 (2004-07-01), Lin
patent: 6759883 (2004-07-01), Gomm
patent: 6774687 (2004-08-01), Gomm et al.
patent: 6781861 (2004-08-01), Gomm et al.
patent: 6803826 (2004-10-01), Gomm et al.
patent: 6850107 (2005-02-01), Gomm
patent: 6853225 (2005-02-01), Lee
patent: 6924686 (2005-08-01), Kirsch
patent: 6982579 (2006-01-01), Lee
patent: 7095261 (2006-08-01), Drexler et al.
patent: 2002/0190766 (2002-12-01), Waldrop
patent: 2003/0081472 (2003-05-01), Lin
patent: 2004/0041606 (2004-03-01), Kirsch
patent: 2004/0044918 (2004-03-01), Dermott et al.
patent: 2004/0057331 (2004-03-01), Graaf
patent: 2005/0062510 (2005-03-01), Zarate et al.
patent: 2005/0116751 (2005-06-01), Lin
patent: 2005/0122153 (2005-06-01), Lin
Saeki et al., “A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, pp. 1656-1668, (1996).
Shim et al., “An Analog Synchronous Mirror Delay for High-Speed DRAM Application,” IEEE Journal of Solid-State Circuits, vol. 34 No. 4, pp. 484-493, (1999).
Kim et al., “A Low-Jitter Mixed-Mode DLL for High-Speed DRAM Applications,” IEEE Journal of Solid-State Circuits, vol. 35 No. 10, pp. 1430-1436, (2000).
Bell Debra M
Drexler Adrian J
Gomm Tyler J
Lee Seong-Hoon
Chasan Michael J.
Lam Tuan T.
Micro)n Technology, Inc.
Ropes & Gray LLP
LandOfFree
Clock capture in clock synchronization circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock capture in clock synchronization circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock capture in clock synchronization circuitry will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2790554