Clock buffer with DC offset suppression

Details Clock buffer with DC offset suppression Clock buffer with DC offset suppression

2001-05-24

2003-10-14

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S312000, C327S563000, C330S260000, C330S282000

Reexamination Certificate

active

06633191

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to buffer circuits, and more particularly to differential buffers for high frequency clock signals.
Buffer circuits are often utilized in integrated circuits. Buffer circuits provide a variety of functions. These functions include transitioning signals from one voltage level to another, such as near the input or output of a device, presenting a known load to a signal transmitter, such as an input to a cell, or providing increased drive for a signal, particularly signals which must be transmitted over significant distances within an integrated circuit.
Some signals are extensively routed with integrated circuits. An example of such a signal is a clock signal. Clock signals are usually distributed using clock trees throughout relatively large areas within integrated circuits. Clock signals are distributed as much of the integrated circuit is synchronously clocked, all using the same clock signal. Clock signals in a clock tree are often sent through buffers separated periodically in space to reduce signal attenuation through transmission. A single clock signal, therefore, may pass through a number of clock buffers.
Differential buffers are often used to buffer high speed clock signals. Many noise sources are common-mode in nature, and differential buffers have good common-mode rejection. In addition, differential buffers often provide improved switching performance, in part because differential buffers may have smaller noise margins allowing for small voltage swings between signal levels.
Preferably, the output signals of a differential buffer do not exhibit drift from one another. When used with a clock signal, for example, the output signals should have the same DC level. Generally, however, resistors and transistors in a differential buffer tend to be slightly mismatched. These mismatches may result in some non-common-mode signal drift. Moreover, differential buffers are often low-pass circuits. Any non-common-mode signal drift, therefore, is likely to be amplified to a greater extent than signal components about a clock frequency. This may result in duty cycle distortion or even effective loss of the clock signal, particularly for high frequency clock signals and long clock buffer trees.
SUMMARY OF THE INVENTION
The present invention provides a clock buffer with dc offset suppression. In one embodiment the invention comprises a differential amplifier, a voltage follower, and a negative feedback circuit. The differential amplifier receives a differential signal and generates an intermediate differential output signal. The voltage follower receives intermediate differential output signal and generates a differential output. The negative feedback circuit receives the differential output and provides negative feedback for the intermediate differential output signal. In one embodiment, the negative feedback circuit comprises a further differential amplifier and two resistive elements. The differential amplifier comprises a first pair of transistors, each receiving one of the differential outputs at their gates after the differential outputs are passed through one of the two resistive elements. In a still further embodiment, the buffer includes a steering circuit coupled to the differential output, the steering circuit steering current from the output of the differential output being pulled low.
In a further embodiment, the invention comprises a differential clock buffer. The differential clock buffer includes an input differential amplifier receiving an input differential clock signal and forming an intermediate differential signal. A differential signal driver receives the intermediate signal and provides an output differential clock signal. The invention further includes means for providing feedback to the intermediate signal using the output differential clock signal. In a further embodiment, the means for providing feedback provides greater negative feedback at low frequencies than at frequencies about the frequency of the input differential clock signal, and more particularly positive feedback at frequencies about the frequency of the input clock signal.
In a still further embodiment, the invention comprises a method of buffering differential clock signals. The method includes receiving a differential clock signal, and forming an intermediate differential clock signal using the differential clock signal. The invention further comprises forming an output differential clock signal using the intermediate differential clock signal and providing feedback to the intermediate clock signal.
These and other aspects of the present invention will be more fully appreciated in view of the attached figures briefly described below and the following detailed description.


REFERENCES:
patent: 4276485 (1981-06-01), Rydval
patent: 4437171 (1984-03-01), Hudson et al.
patent: 4739198 (1988-04-01), Maruyama
patent: 4754171 (1988-06-01), Dasai et al.
patent: 4970406 (1990-11-01), Fitzpatrick et al.
patent: 4999520 (1991-03-01), Usami et al.
patent: 5057701 (1991-10-01), Miller, Jr.
patent: 5059829 (1991-10-01), Flannagan et al.
patent: 5274284 (1993-12-01), Krenik et al.
patent: 5313120 (1994-05-01), Pelley, III
patent: 5376898 (1994-12-01), Tanaka et al.
patent: 5512853 (1996-04-01), Ueno et al.
patent: 5602498 (1997-02-01), Satoh et al.
patent: 5652545 (1997-07-01), Miyashita et al.
patent: 5754062 (1998-05-01), Satoh et al.
patent: 5796278 (1998-08-01), Osborn et al.
patent: 5818278 (1998-10-01), Yamamoto et al.
patent: 5903175 (1999-05-01), Miyashita
patent: 6011436 (2000-01-01), Koike
patent: 6018261 (2000-01-01), Alford et al.
patent: 6023181 (2000-02-01), Penny et al.
patent: 6118333 (2000-09-01), Oda
patent: 6160422 (2000-12-01), Huang
patent: 6181182 (2001-01-01), Stotz et al.
patent: 6208177 (2001-03-01), Knoedl, Jr.
patent: 6211722 (2001-04-01), Mattia et al.
patent: 02 071612 (1990-03-01), None
patent: WO 01/03300 (2001-01-01), None
Sasaki, et al., “A New Emitter-Follower Circuit for High-Speed and Low-Power ECL,” IEICE Trans. Electron vol. E78-C No. 4, pp. 374-379, Apr. 1995.

Affiliated with

Also associated with

Rating

Clock buffer with DC offset suppression does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock buffer with DC offset suppression, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock buffer with DC offset suppression will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3113126