Clock buffer with adjustable delay and fixed duty cycle output

Details Clock buffer with adjustable delay and fixed duty cycle output Clock buffer with adjustable delay and fixed duty cycle output

1990-12-28

1992-10-20

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307262, 307265, 328 63, 328155, H03K 513, H03K 504

Patent

active

051572770

ABSTRACT:
A clock buffer circuit for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL). The switching level of the differential input buffer is adjustable, either by adjusting the DC bias applied to the input clock signal, or by adjusting the reference signal, which changes the point in the cycle of the input clock signal at which the differential buffer switches. The PLL synchronizes its output to an edge of the output of the differential buffer, but maintains the same duty cycle (e.g., 50%). Accordingly, the clock buffer circuit may have its delay adjusted, by modifying a voltage divider, applying a variable voltage, or programmably via a digital-to-analog converter, to match the delays of other clock buffer circuits in the computer system, reducing the clock skew in the system. A sine wave may be used as the input clock signal, so that harmonic noise is reduced in the system.

REFERENCES:
patent: 4494021 (1985-01-01), Bell et al.
patent: 4737724 (1988-04-01), Porrot
patent: 4837464 (1989-06-01), Viscardi et al.
patent: 4864160 (1989-09-01), Abdoo
Johnson et al., "A Variable Delay Line PLL for CPU-Coprocessor Synchronization", J. Solid State Circuits, vol. 23, No. 5, (IEEE, Oct. 1988), pp. 1218-1223.
Jeong et al., "Design of PLL-Based Clock Generation Circuits", J. Solid State Circuits, vol. SC-22, No. 2, (IEEE, Apr. 1987), pp. 255-261.

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