Clock buffer circuit having predetermined gain with bias...

Details Clock buffer circuit having predetermined gain with bias... Clock buffer circuit having predetermined gain with bias...

2007-11-20

2007-11-20

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S563000, C330S261000

Reexamination Certificate

active

11210757

ABSTRACT:
Implementing maintenance of a higher speed with fewest possible additional circuits while suppressing deterioration in characteristics of a clock buffer caused by an offset voltage. In a clock buffer circuit comprising a differential amplifier including a pair of load resistances, a pair of differential stage transistors, a constant current source transistor for supplying an operating current to the differential stage transistors, and a bias circuit for supplying to the constant current source transistor a bias voltage according to the resistance value of the load resistances, the bias circuit generates the bias voltage so controlled that the voltage gain of the clock buffer circuit becomes a predetermined value with respect to a variation of the resistance value of the load resistances.

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