Clock boosting systems and methods

Details Clock boosting systems and methods Clock boosting systems and methods

2009-03-20

2011-12-27

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S113000, C716S116000

Reexamination Certificate

active

08086986

ABSTRACT:
In one embodiment of the invention, a programmable logic device (PLD) includes logic blocks, registers corresponding to the logic blocks, and configuration memory adapted to store configuration data for configuring the PLD. Also included in the PLD is a general routing network having a plurality of routing wires and a clock distribution network having a plurality of routing wires. At least one clock signal path is provided within the PLD from a clock source to one of the registers via a routing wire of the clock distribution network and a routing wire of the general routing network.

REFERENCES:
patent: 7362135 (2008-04-01), Chang

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