Clock architecture for synchronous system bus which regulates an

Details Clock architecture for synchronous system bus which regulates an Clock architecture for synchronous system bus which regulates an

1994-06-30

1997-04-29

Heckler, Thomas M.

G06F 110

Patent

active

056258054

ABSTRACT:
A synchronous computer system is described. The system is a multiprocessor system having a bus system clock and a processor clock for each processor. The system includes a synchronous computer system bus and a plurality of circuit modules coupled to the synchronous bus with at least two of the modules having at least one processor, with the processor modules having the at least one processor which runs asynchronously to each of the other processors while the processor modules are synchronous to the system bus. The system further includes clock generator means for providing a corresponding plurality of clock signals and a plurality of conductors coupled between said clock generating means and said plurality of modules. Each of said conductors have electrical paths with substantially the same electrical path length, with each one of said modules further including means, coupled to a corresponding one of said conductors and disposed on said module, for regulating and adjusting skew between clock signals on said module.

REFERENCES:
patent: 5040109 (1991-08-01), Bowhill et al.
patent: 5083100 (1992-01-01), Hawkins et al.
patent: 5164677 (1992-11-01), Hawkins et al.
patent: 5272390 (1993-12-01), Watson, Jr. et al.
patent: 5309035 (1994-05-01), Watson, Jr. et al.
patent: 5369640 (1994-11-01), Watson et al.

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