Clock and data recovery with extended integration cycles

Pulse or digital communications – Receivers

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C455S230000

Reexamination Certificate

active

07486746

ABSTRACT:
Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, where each integrator is sampled at or near the middle of its two-UI integration cycle. In an exemplary 10-GHz system, the reset cycle of each integrator may begin many tens of picoseconds after the data is sampled. Since the signal is sampled near the center of the integration cycle and is not highly proximate to the time of the integrator reset, the latch signal has a window of uncertainty extending into the length of a data bit cell with little possibility of latching erroneous data. The sensitivity of the clock recovery circuitry may be optimized by centering the latch function over the time of highest signal level, thereby maximizing signal-to-noise ratio.

REFERENCES:
patent: 5090026 (1992-02-01), Stern et al.
patent: 5832027 (1998-11-01), Ishigaki
patent: 5953370 (1999-09-01), Durrant et al.
patent: 6091688 (2000-07-01), Tanoue et al.
patent: 6154487 (2000-11-01), Murai et al.
patent: 6301291 (2001-10-01), Rouphael et al.
patent: 6516185 (2003-02-01), MacNally
patent: 7209525 (2007-04-01), Laturell et al.
patent: 2002/0025012 (2002-02-01), Saito et al.
patent: 2002/0031093 (2002-03-01), Gfeller et al.
patent: 2002/0159542 (2002-10-01), Kokkonen et al.
patent: 2003/0101396 (2003-05-01), Price
patent: 2004/0066842 (2004-04-01), McCorkle
patent: 2004/0091028 (2004-05-01), Aronson et al.
“A Semidigital Dual Delay-Locked Loop” by Stefanos Sidiropoulous and Mark A. Horowitz, IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1683-1692.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Clock and data recovery with extended integration cycles does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock and data recovery with extended integration cycles, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock and data recovery with extended integration cycles will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4129285

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.