Clock-and-data-recovery system having a multi-phase clock...

Details Clock-and-data-recovery system having a multi-phase clock... Clock-and-data-recovery system having a multi-phase clock...

2005-08-08

2009-10-06

Ghayour, Mohammad H (Department: 2611)

Pulse or digital communications

Synchronizers

Self-synchronizing signal

C326S093000, C365S233100, C370S395620, C370S518000, C398S155000

Reexamination Certificate

active

07599457

ABSTRACT:
In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.

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“Data Recovery,” by Nick Sawyer, Xilinx, XAPP224, v2.4, Jan. 24, 2005.

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