Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator
Reexamination Certificate
1999-04-29
2001-04-03
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural a.f.s. for a single oscillator
C331S00100A, C331S012000, C375S376000, C327S147000
Reexamination Certificate
active
06211741
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a linear clock and data recovery circuits generally and, more particularly, to a circuit and/or method that may recover one or more half-rate clock signals from a serial input data stream.
BACKGROUND OF THE INVENTION
Phase-Lock Loops (PLLs) are circuits that may be used to recover clock signals from serial data-bit streams and/or to generate re-timed data. As operating speeds of clock and data recovery circuits increases, the design of PLL components (e.g., a voltage-controlled oscillator (VCO), a phase-detector (PD) and/or a divider) becomes more complicated and consumes more power. Some architectures use multiple phases of a lower-rate clock but feature non-linear characteristics or reduced linear range.
Referring to
FIG. 1
, a circuit
10
is shown illustrating a conventional data recovery circuit. The circuit
10
generally comprises phase detector
12
, a phase frequency detector
14
, a divider
16
, a VCO
18
and a CPF
20
.
The VCO
18
generates a full-rate clock which is divided by “N” by the divider FBDIV
16
. The divided down clock signal CLK_DIV is presented to the phase-frequency detector
14
. The PFD
14
also receives a reference clock signal REFCLK_IN which is typically a divided by N version of the data signal. The PFD
14
compares the signals REFCLK_IN and CLK_DIV and generates a pump-up and a pump-down signal. The pump-up and pump-down signals are presented to the charge-pump/filter
20
through a multiplexer controlled by a signal LLC. The signal LLC controls the “locking” of the circuit
10
to the signal REFCLK_IN or the signal DATA. When the circuit
10
is frequency locked to the signal REFCLK, the multiplexer
22
is switched to select the signal DATA (through the PD
12
) for the closed loop by using the signal LLC. The close loop-with the PD
12
then locks the signal DATA and generates recovered data and clock signals. This implementation requires the use of a full-rate PD
12
and a full-rate VCO
18
. The VCO
18
generates a single phase of the clock. The divider FBDIV
16
is also a full-rate single-phase divider.
The circuit
10
has the disadvantage that is (i) requires full rate components such as the phase-detector and the VCO, (ii) requires a linear full-rate phase-detector, and/or (iii) has a full-rate operation that implies higher power components are required.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a clock circuit. The first circuit may be configured to generate an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal. The clock circuit may be configured to generate the first and second clock signals in response to the output signal.
The objects, features and advantages of the present invention include providing a data recovery circuit that may (i) enable higher data rate linear PLLs in existing integrated-circuit technologies (for a given performance level), (ii) be implemented using half-rate components that may consume less power, (iii) be implemented with linear phase-detectors having extended linear range that may provide better jitter performance, (iv) provide a clock and data recovery PLL utilizing a half-rate clock and its quadrature, (v) provide a PLL utilizing a half-rate clock and its quadrature with linear phase-difference vs. gain characteristics, (vi) provide a linear PLL comprising two phase detectors each working on one edge of data, (vii) provide a PLL comprising three charge pumps circuits (e.g., two for each of the two phase detectors and one for the PFD) and/or (viii) provide a PLL comprising a four phase quarter rate VCO and XOR gates to generate respective half-rate clocks.
REFERENCES:
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patent: 5138281 (1992-08-01), Boudewijns
patent: 5384551 (1995-01-01), Kennedy et al.
patent: 5436938 (1995-07-01), Pigeon
patent: 6075416 (2000-06-01), Dalmia
A 0.8-&mgr;m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links, By: Chih-Kong Ken Yang and Mark A. Horowitz, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 2015-2023.
FP 15.3: A 1.25Gb/s, 460 mW CMOS Transceiver for Serial Data Communication, By: Dao-Long Chen, Michael O. Baker, 1997 IEEE International Solid-State Circuits Conference, pp. 242-243.
FP 15.1: A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis, By: Alan Fiedler, Ross Mactaggart, James Welch, Shoba Krishnan, 1997 IEEE International Solid-State Circuits Conference, pp. 238-239.
Mohammad Navabi et al., U.S.S.N. 08/878,714 Phase Locked Loop (PLL) with Linear Parallel Sampling Phase Detector, filed Jun. 19, 1997.
Mohammad Navabi et al., U.S.S.N. 08/879,287, Phase Detector with Linear Output Response, filed Jun. 19, 1997.
Kamal Dalmia, U.S.S.N. 09/302,213, Phase Detector with Extended Linear Range, filed Apr. 29, 1999.
Kamal Dalmia, U.S.S.N. 09/283,058, Method, Architecture and Circuit for Half-Rate Clock and/or Data Recovery, filed Apr. 1, 1999.
Kamal Dalmia et al., U.S.S.N. 09/216,465, Phase Detector, filed Dec. 18, 1998.
Cypress Semiconductor Corp.
Kinkead Arnold
Maiorana P.C. Christopher P.
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