Clock and data recovery phase-locked loop

Details Clock and data recovery phase-locked loop Clock and data recovery phase-locked loop

2005-12-20

2005-12-20

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Transceivers

C375S374000, C375S375000, C375S376000

Reexamination Certificate

active

06977959

ABSTRACT:
A clock recovery circuit that operates at a clock speed equal to one-half the input data rate is presented. The clock recovery circuit uses dual input latches to sample the incoming serial data on both the rising edge and falling edge of a half-rate clock signal to provide equivalent full data rate clock recovery. The clock recovery circuit functions to maintain the half-rate clock transitions in the center of the incoming serial data bits. The clock recovery circuit includes a phase detector, charge pump, controlled oscillation module and a feedback module. The phase detector produces information on the phase and data transitions in the incoming data signal to the charge pump. Generally, the circuit is delay insensitive and receives phase and transition information staggered relative to each other.

REFERENCES:
patent: 5329559 (1994-07-01), Wong et al.
patent: 5483558 (1996-01-01), Leon et al.
patent: 6034554 (2000-03-01), Francis et al.
patent: 6356160 (2002-03-01), Robinson et al.
patent: 2002/0021470 (2002-02-01), Savoj
patent: 2003/0001557 (2003-01-01), Pisipaty
Jafar Savoj, Behzad Razavi; “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector”; IEEE 2001; IEEE Journal of Solid-State Circuits, vol. 36, No. 5; May 2001; pp. 761-767.

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