Clock and data recovery method and corresponding device

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07978801

ABSTRACT:
A clock and data recovery method comprising the following steps: an oversampling step wherein an oversampled stream of samples is generated from an input data stream at a data rate by using reference clock signal at a clock rate, the clock rate being higher than the data rate, and a tracking step of the input data stream realised by locating transitions between adjacent samples of the oversampled stream and by moving a no transition area within the oversampled stream wherein no transitions between adjacent samples are found a recovered data signal being obtained as a central portion of the no transition area and a recovered clock signal being obtained by dividing the reference clock signal. A clock and data recovery device is also described.

REFERENCES:
patent: 4949051 (1990-08-01), Viola
patent: 5812619 (1998-09-01), Runaldue
patent: 6611219 (2003-08-01), Chen et al.
patent: 6650661 (2003-11-01), Buchanan et al.
patent: 6694462 (2004-02-01), Reiss et al.
patent: 7409031 (2008-08-01), Lee et al.
patent: 2002/0099987 (2002-07-01), Corbin et al.
patent: 2003/0115542 (2003-06-01), Hwang et al.
patent: 2004/0202261 (2004-10-01), Gregorius
patent: 2004/0202266 (2004-10-01), Gregorius et al.
patent: 2005/0069071 (2005-03-01), Kim et al.
patent: 2005/0078782 (2005-04-01), Dunning et al.
patent: 2005/0286643 (2005-12-01), Ozawa et al.
patent: 2006/0109942 (2006-05-01), Vallet
patent: 1 209 842 (2002-05-01), None
Lai, B. et al., “A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit,”ISSCC Dig. Tech. Papers, Feb. 14, 1991, pp. 144-145.
Park, J.-Y. et al., “A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method,”IEICE Trans. Fundamentals, vol. E83-A, No. 6, Jun. 2000, pp. 1100-1105.
Poulton, J. et al., “A Tracking Clock Recovery Receiver for 4-Gbps Signaling,”IEEE Micro, vol. 18, Issue 1, Jan./Feb. 1998, pp. 25-27.
Rhee, W. et al., “A Semi-Digital Delay-Locked Loop Using an Analog-Based Finite State Machine,”IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, Issue: 11, Nov. 2004, pp. 635-639.
Sun, Sam Y., “An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance,”IEEE Journal of Solid-State Circuits, vol. SC-24, Apr. 1989, pp. 325-330.
Yang, C.-K. K., et al., “A 0.5-μm CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling,”IEEE Journal of Solid-State Circuits, vol. 33 No. 5, May 1998, pp. 713-722.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Clock and data recovery method and corresponding device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock and data recovery method and corresponding device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock and data recovery method and corresponding device will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2632142

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.